Transcript Lecture_1_Introduction_48

Introduction
Mohammad Sharifkhani
The IC Growth Cycle
Technology
advances
Consumption
grows
Density
Applications
Performance
Devices
Switching energy
Users
Cost per function
Revenue
Money!
Chen, ISSCC’07
Market share
Logic is there all the time
Moore’s Law - 1965
Transistors
Per Die
“Reduced cost is one of the big
attractions of integrated
electronics, and the cost
advantage continues to increase
as the technology evolves
toward the production of larger
and larger circuit functions on a
single semiconductor substrate.”
Electronics, Volume 38,
Number 8, April 19, 1965
1010
109
108
107
106
105
104
103
1965 Data (Moore)
102
101
100
1960
1965
1970
1975
1980
1985
1990
1995
2000
2005
2010
Source: Intel
Moore’s Law - 2005
Transistors
Per Die
1010
1G
109
108
107
106
105
104
1K
103
102
2G
512M
256M
128M
Itanium™ 2 Processor
64M
Itanium™ Processor
16M
Pentium® 4 Processor
4M
Pentium® III Processor
1M
Pentium® II Processor
256K
Pentium® Processor
64K
486™ Processor
16K
386™ Processor
4K
80286
8080 8086
8008
1965 Data (Moore)
4004
Memory
101
Microprocessor
100
1960
1965
1970
1975
1980
1985
1990
1995
2000
2005
2010
Source: Intel
Silicon Scaling Still Improves
Density, Performance, Power, Cost
130 nm
Madison
Cores/Threads
1/1
Transistors
0.41
L3 Cache
6
Frequency
1.5
Relative Performance
1
Thermal Design Power
130
90 nm
Montecito
2/4
1.72 Billion
24 MByte
>1.7 GHz
>1.5x
~100 Watt
Source: Intel
Gate Count
Design Cost
New tech. node model
R&D Cost
Facilities development cost
Revenues
Revenue
Key Points
• Moore’s Law thriving after 40 years
• Convergence drives IC industry growth
• Integrated platforms optimize user
experience
• Multi-core parallelism going mainstream
Convergence Drives Growth
Convergence
Convergence
Wireless Mobile PC
% of Notebooks
that have Wireless
100
90
96
65
50
10
0
2003
2004
2005
2006
Source: IDC
Convergence
Data Phones and Traffic
2004: Data Phones
Cross-over Voice
Data Traffic: 56% Annual
Growth thru 2006
New Cell Phone Sales by Feature Set
800
600
500
400
300
Data
Voice
Bits of Traffic
Million units
700
Data
200
100
Voice
0
2002 2003 2004 2005 2006 2007 2008 2009
Source: WebFeet Research
2001
2006
Source: Goldman Sachs and Co., McKinsey & Company; Dec. 2002
Convergence
Digital Consumer Electronics
The Great Crossover
Digital Technologies Surpass Analog
Camera Sales
Millions
TVs
Cameras
Camcorders
DVD Players
25
20
15
10
5
Cell Phones
Satellites
0
’95 ’96 ’97 ’98 ’99 ’00 ’01 ’02 ’03 ’04 ’05
‘95
‘96 ‘97 ‘98 ‘99 ‘00 ‘01 ‘02 ‘03 ‘04 ‘05
Portable CD Players
’95 ’96 ’97 ’98 ’99 ’00 ’01 ’02 ’03 ’04 ’05 ’06 ’07 ’08
Crossover Year
Sources: Consumer Electronics Association, Photo Marketing Association International,
Photofinishing News, SBCA/Sky Trends
Key Points
• Moore’s Law thriving after 40 years
• Convergence drives IC industry growth
• Integrated platforms optimize user
experience
• Multi-core parallelism going mainstream
Demand Growth Driven by
Better User Experiences
Security
Virtualization
User
Multitasking
Experience
Manageability
Ease of Use
Battery Life
Compactness
Wireless Mobility
Multimedia
Networking
Graphics
Computing
Memory
Platforms Optimize User
Experience
Comms and
WiFi
Example: Intel platforms
User
Experience
ProSet
Low Power
PCI-E
Infiniband
Serial ATA
AGP 8X
USB 2.0
IAPC
Low
AGP 4X
power
Itanium
Math
USB
Architecture
Coprocessor
SSE2
AGP 2X
Speedstep
Integrated
SSE
Itanium™
Cache
PCI MMX Quickstart
Pentium®III processor Pentium®4
Multiple
Processor
Xeon™
Execution Units
with HT
processor
386
Pentium® Pentium®II Pentium®III Pentium®III
mobile Pentium®4
processor processor
processor processor processor
processor
Graphics
Software
Capabilities
Chipset
Capabilities
HD Audio
Multi Core
HyperThreading
Virtualization
Innovate and Integrate
Processor
Capabilities
Itanium™2
processor
Xeon™
processor
Pentium®4
mobile
processor
Base
Performance
RMS Applications Growing
Emerging workloads increase need for
high performance parallel processing
Efficiency
Increase with Parallel
100
Architecture
Relative
processor
performance*
Dual / Multi-Core
(constant power
envelope)
10X
10
Single-Core
3X
1
2000
2004
2008+
FORECAST
*Average of SPECInt2000 and SPECFP2000 rates for Intel desktop processors
vs initial Intel® Pentium® 4 Processor
Source: Intel
Multi-Core Parallelism Going
Mainstream
Dual-Core Processor Plans (Intel)
Servers
Desktop
90nm
Montecito
(2005)
90nm
Smithfield
(2005)
90nm
Server Processor
(2006)
65nm
Desktop Processor
(2006)
Mobile
65nm
Yonah
(2005)
Note: Die images not to scale and may not depict actual product
Source: Intel
Key Points
• Moore’s Law thriving after 40 years
• Convergence drives IC industry growth
• Integrated platforms optimize user
experience
• Multi-core parallelism going mainstream
• Holistic solutions deliver power efficiency
Silicon Technology Changes to
Increase Power Efficiency
•
•
•
•
•
1960’s:
1970’s:
1980’s:
1990’s:
2000’s:
Bipolar
PMOS, NMOS
CMOS
Voltage scaling (P = CV2f)
Power efficient scaling/design
Power Efficient 90nm Transistors
with Strained Silicon
PMOS
SiGe
High
Stress
Film
NMOS
SiGe
Compressive channel strain
30% drive current increase
Tensile channel strain
10% drive current increase
does not raise transistor leakage
Innovate and integrate
for cost effective production
Source: Intel
Strained Silicon Improves
Transistor Performance and/or
Reduces Leakage
1000
Std
Transistor 100
Leakage
Current
(nA/um)
Strain
Std
+25% I ON
Strain
+10% I ON
0.20x I OFF
10
0.04x I OFF
PMOS
NMOS
1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Transistor Drive Current (mA/um)
Source: Intel
Advances in Power Efficient
Design
350
Cache Switch
Cache Igate
300
Cache Ioff
Power
250
(W)
Core Switch
Core Igate
200
Core Ioff
IO bias
150
ISSCC 2005 P10.1
“The Implementation of
a 2-core Multi-Threaded
ItaniumTM Family
Processor”
DCAP lkg
100
50
0
Using
prior
design
techniques
Simple Port of Madison
Montecito Final
With
new
power
reduction
techniques
Circuit Techniques Reduce
Source Drain Leakage
Body Bias
Vdd
Stack Effect
Sleep Transistor
Vbp
+ Ve
Equal Loading
Logic
Block
- Ve
Vbn
Leakage
Reduction
2 - 10X
2 - 10X
2 - 1000X
Sleep Transistor Reduces SRAM
Leakage Power
VDD
70 Mbit SRAM leakage current map
SRAM
Cache
Block
NMOS
Sleep
Transistor
Accessed block
VSS
Without sleep transistor
With sleep transistor
>3x SRAM leakage reduction on inactive blocks
Source: Intel
Sleep Transistors Reduce ALU Leakage
Vcc
external
Sleep transistors
PMOS underdrive Vcc
PMOS
Sleep
Body
Bias
Scan
out
PMOS overdrive Vss
Virtual Vcc
Scan
FIFO Sleep
ALU
ALU
Body
Bias
Dynamic
ALU
Sleep transistor
and body bias
control
Scan
32
Scan
capture
control
ALU core
NMOS overdrive Vcc
Control
Body bias
37X leakage reduction
demonstrated on test chip
Virtual Vss
3-bit A/D
NMOS underdrive Vss
Vssexternal
Source: ISSCC 2003, Paper 6.1
What happens to Analog guys?
In the nanoelectronics era CMOS
performance will exceed that of the SiGe
HBT
Power Consumption Relative to a 2002 PC
Holistic Approach to System Power
3
Projected Change in Peak Power Consumption
of High-End Desktop Computers
Power Supply
2.5
Other
20%
VRMs
2
Graphics Card
Processor
1.5
30%
41%
1
43%
23%
0.5
10%
0
2002
57%
2004
2005 (est.)
70%
80%
Projected power supply efficiency
Source: Intel
Key Points
• Moore’s Law thriving after 40 years
• Convergence drives IC industry growth
• Integrated platforms optimize user
experience
• Multi-core parallelism going mainstream
• Holistic solutions deliver power efficiency
• Nanotechnology will extend IC advances
• Lithography innovations remain vital
Silicon Technology Reaches
Nanoscale
10
10000
Nominal feature size
1
0.7X every
2 years
130nm
Micron
90nm
Gate Length
65nm
45nm
32nm
22nm
0.1
Nanotechnology
(< 100nm)
0.01
1970
1970
1980
1980
1000
Nanometer
100
70nm
50nm
35nm
25nm
18nm
12nm
1990
1990
2000
2000
10
2010
2010
2020
2020
Source: Intel
Nanotechnology Hallmarks
(For Nanoelectronics)
• Structures measured in nanometers
– Less than 0.1-micron (100nm)
• New processes, materials, device structures
– Incrementally changing silicon technology base
• Materials manipulated on atomic scale
– In one or more dimensions
• Increasing use of self-assembly
– Using chemical properties to form structures
Nanotechnology innovations will extend
silicon technology and Moore’s Law
Design Your Own Film with
Atomic Layer Deposition (ALD)
B
A
A
Step 1
Step 3
B
A
A
Step 2
Step 4
Atomic level manipulation + Self-assembly
ALD Enables High-k Dielectric
to Reduce Gate Leakage
Gate
Gate
3.0nm High-k
1.2nm SiO2
Silicon substrate
Gate capacitance
Gate dielectric
leakage
Silicon substrate
High-k vs. SiO2
Benefit
60% greater
Faster transistors
> 100x reduction
Lower power
Process integration is the key challenge
Source: Intel
Nanostructures for the Next Decade
(Transistor Research at Intel)
(a)
(b)
Source
Drain
Si Device
Miniaturization
Drain
Lg =
Gate
10 nm
CNT
Source
Single-wall
D = 1.4 nm
Drain
Source
Gate
Si
body
(d) Drain
(Pd)
(c)
(c)
III-V Device
Research
Non-planar
Tri-Gate
Architecture
Multi
epitaxial
layers
Lg = 75 nm
Gate
Source
Carbon
Nanotube
Transistor
Gate
(Pt)
Source
Source: Intel
Benchmarking Nanotransistor
Progress
GATE DELAY CV/I [ps]
100
NMOS
10
1
Si MOSFETs
CNT FETs
III-V FETs
0.1
1
10
100
1000
GATE LENGTH LG [nm]
10000
Source: Intel compilation of published data
Lithography Must Break Through
to Shorter Wavelength (EUV* @ 13.5nm)
1000
nm
* Extreme Ultraviolet
Feature size
248nm
100
Lithography
Wavelength
193nm & extensions
Gap
EUV
10
’ 89 ’91 ’93 ’95 ’97 ’99 ’01 ’03 ’05 ’07 ’09 ’11
Source: Intel
EUV Lithography in
Commercial Development
EUV MET Image (8/04)
EUV Micro exposure tool (MET)
•
•
•
•
•
Integrated development in progress
Source power and lifetime
Defect free mask fabrication and handling
Optics lifetime
Resist performance
Source: Intel
Key Points
•
•
•
•
•
•
•
•
•
Moore’s Law thriving after 40 years
Convergence drives IC industry growth
Integrated platforms optimize user experience
Multi-core parallelism going mainstream
Holistic solutions deliver power efficiency
Nanotechnology will extend IC advances
Lithography innovations remain vital
Moore’s Law will outlive CMOS
Future rides on innovation and integration
Moore’s Law Will Outlive CMOS
10µm
1µm
1013 Bipolar PMOS NMOS
1012
1011
Transistors/Die
1010
109
108
CMOS Voltage
Scaling
10nm
100nm
Pwr Eff
Scaling
New Nanostructures
Beyond CMOS?
Spin based?
Molecular?
Other?
1965 Data (Moore)
Memory
Microprocessor
107
106
105
104
103
102
101
100
Mega
Xtor
Kilo
Xtor
1960
1970
1980
1990
Giga
Xtor
2000
Tera
Xtor
2010
2020
2030
Innovation and Integration
Will Sustain Moore’s Law
Innovation
Integration
Identify needs and
create capabilities
that drive growth
Deliver platforms
to optimize user
experience
Anticipate barriers
and seek timely
breakthroughs
Integrate new
materials, devices,
processes
Make strategic
technology
transitions
Coordinate
strategic shifts
across industry