Transcript Status Register

Chapter 10
Input/Output Interface
Circuits and LSI Peripheral
Devices
Chapter nine covers the following topics:
10.1 Core and Special-Purpose I/O Interfaces
10.2 Byte-Wide Output Ports Using Isolated I/O
10.3 Byte-Wide Input Ports Using Isolated I/O
10.4 Input/Output Handshaking and a Parallel Printer Interface
10.5 82C55A Programmable Peripheral Interface
10.6 82C55A Implementation of Parallel Input/Output Ports
10.7 Memory-Mapped Input/Output Ports
10.8 82C54 Programmable Interval Timer
10.9 82C37A Programmable Direct Memory Access Controller
10.10 Serial Communications Interface
10.11 Programmable Communication Interface Controllers
10.12 Keyboard and Display Interface
10.13 8279 Programmable Keyboard/Display Controller
10.1 CORE AND SPECIAL-PURPOSE I/O INTERFACES
Special-Purpose I/O Interfaces
Keyboard, Display, Parallel Printer Interface, LAN Interface,
They are referred to as special-purpose interfaces because not all
microcomputer systems employ each of these types.
They are all implemented in the original PC as add-on cards
Core Input/Output Interfaces
Parallel input/output ports, interval timers, and direct memory
access control
Interfaces that are also considered to be part of the I/O subsystem.
These I/O functions are employed by most microcomputer systems
IO.2 BYTE-WIDE OUTPUT PORTS USING ISOLATED I/O
For 8088
IO.2 BYTE-WIDE OUTPUT PORTS USING ISOLATED I/O
address of port 0 is
10000000000000002= 800016
However, if these bits are all
made equal to 1 instead of 0,
the address is
11111111111100002 =FFF016
other examples are
8FF016 and F00016
Check examples 10.1 & 10.2
IO.2 BYTE-WIDE OUTPUT PORTS USING ISOLATED I/O
For 8086
Time-Delay Loop and Blinking an LED at an output port
Time-Delay Loop and Blinking an LED at an output port
Sequence of instructions needed to initialize0 7 to logic 0.
ON_OFF:
MOV DX, 8000H
MOV AL, 00H
OUT DX, AL
;Initialize address of port 0
;Load data with bit 7 as logic 0
;Output the data to port 0
delay for a short period of time so as to maintain the data
written to the LED
HERE:
MOV CX, 0FFFFH
LOOP HERE
;Load delay count of FFFFH
;Time delay loop
the value in bit 7 of AL is complemented to 1 and then a jump
is performed to return to the output operation that writes the
data to the output port:
XOR AL, 80H
JMP ON_OFF
;Complement bit 7 of AL
;Repeat to output the new bit 7
10.2 BYTE-WIDE INPUT PORTS USING ISOLATED I/O
Polling technique
In practical applications, it is sometimes necessary within an I/O
service routine to repeatedly read the value at an input line and
test this value for a specific logic level.
Let us assume that we want to read the contents of port 0, and
that input I3 at this port is the line that is being polled.
Polling the Setting of a Switch
10.4 INPUT/OUTPUT HANDSHAKING AND A
PARALLEL PRINTER INTERFACE
In some applications, the microcomputer must synchronize the input
or output of information to a peripheral device.
Two examples of interfaces that may require a synchronized data transfer
are a serial communications interface and a parallel printer interface.
Sometimes it is necessary as part of the I/O synchronization process first
to poll an input from an I/O device and, after receiving the appropriate level
at the poll input, to acknowledge this fact to the device with an output.
This type of synchronization is achieved by implementing what is known
as handshaking as part of the input/output interface.
conceptual view of the interface between the printer and a parallel printer
port. There are three general types of signals at the printer interface:
data, control, and status.
Setting
Busy
check
Data out
Strobe
pulse
Update
Repeat
10.5 82C554 PROGRAMMABLE PERIPHERAL INTERFACE
The 82C55A is an LSI peripheral designed to permit easy
implementation of parallel I/O in the 8088- and 8086-microcomputer
systems.
It provides a flexible parallel interface, which includes features such
as
single-bit, 4-bit, and byte-wide input and output ports: levelsensitive inputs; latched outputs; strobed inputs or outputs; and
strobed bidirectional input/outputs. These features are selected
under software control.
82C55A
82C55A
82C55A
82C55A
Operation Modes of 82C55
Mode 0 selects what is called simple I/O operation where the lines
of the port can be configured as level-sensitive inputs or latched
outputs.
Mode 1 operation represents what is known as strobed I/O. In
this way, the A and B ports are configured as two independent
byte-wide I/O ports, each of which has a 4-bit control/data port
associated with it. The control/data ports are formed from the
lower and upper nibbles of port C, respectively.
Mode 2, represents what is known as strobed bidirectional I/O.
The key difference is that now the port works as either inputs or
outputs and control signals are provided for both functions.
Only port A can be configured to work in this way.
Mode 0 (simple I/O)
Mode 1 (strobed I/O)
In this way, the A and B ports
are configured as two
independent byte-wide I/O
ports, each of which has a 4bit control/data port
associated with it. The
control/data ports are formed
from the lower and upper
nibbles of port C, respectively.
Mode 1 (strobed I/O)
When configured in this way, data applied to an input port must
be strobed in with a signal produced in external hardware. An
output port in mode 1 is provided with handshake signals that
indicate when new data are available at its outputs and when
an external device has read these values.
Strobe input (STBA)
Interrupt request (INTRA)
Input buffer full (IBFA)
Interrupt enable (INTEA)
Acknowledge (ACKA)
Output buffer full (OBFA)
Mode 1 (strobed I/O)
Mode 1 (strobed I/O)
Mode 1 (strobed I/O)
Mode 2 (strobed bidirectional I/O)
The key difference is that now
the port works as either inputs
or outputs and control signals
are provided for both
functions. Only port A can be
configured to work in this way.
bit set/reset feature
Status information for port C
The MPU can be programmed to read the control information
from port C through software. This is known as reading the status
of port C.
The format of the status
information input by reading
port C of an 82C55A operating
in mode 1
The format of the status
information input by reading
port C of an 82C55A operating
in mode 2
By using a software handshake sequence
that tests the status bits to change the
program sequence, hardware signals
such as interrupts can be saved. For
instance, if port A is used as an input in
mode 1, the processor can read (poll) the
status register and check bit D3 for INTRA.
If D3 is 1, INTRA is active and the
processor is signaled to read the data
from port A of the 82C55A. In this way, the
INTRA output may not be connected to the
processor and one interrupt request input
is saved.
10.6 82C55A IMPLEMENTATION OF PARALLEL
INPUT/OUTPUT PORTS
8086 based
10.7 MEMORY- MAPPED INPUT/OUTPUT PORTS
Check the examples in the textbook
10.9
82C37A PROGRAMMABL DIRECT MEMORY
ACCESS CONTROLLER
DMA capability permits devices, such as peripherals, to perform highspeed data transfers between either two sections of memory or between
memory and an I/O device.
In a microcomputer system, the memory or I/O bus cycles initiated as
part of a DMA transfer are not performed by the MPU; instead, they are
performed by a device known as a DMA controller, such as the 82C37A.
The DMA mode of operation is frequently used when blocks or packets of
data are to be transferred. For instance, disk controllers, local area
network controllers, and communication controllers are devices that
normally process data as blocks or packets.
A single 82C37 A, supports up to four peripheral devices for DMA operation
Microprocessor Interface of the 82C37A
Microprocessor Interface of the 82C37A
82C37 A acts as a peripheral controller device, and its operation must
be initialized through software
This is done by reading from or writing into the bits of its internal registers
Whenever the 82C37 A is not in use by a peripheral device for DMA
operation, it is in a state known as the idle state
in this state, the microprocessor can issue commands to the DMA
controller and read from or write to its internal registers
Data bus lines DB0 through DB7 form the path over which these data
transfers take place
Which register is accessed is determined by a 4-bit register address that
is applied to address inputs A0 through A3
During the data-transfer bus cycle, other bits of the address are
decoded in external circuitry to produce a chip-select (CS) input for the
82C37A
DMA interface of the 82C37A
DMA interface of the 82C37A
82C37A contains four independent DMA channels, channel 0 through 3.
Typically, each of these channels is dedicated to a specific peripheral
device.
ln the idle stare. the 82C37A continuously tests these inputs to see if one
is active. When a peripheral device wants to perform DMA operations it
makes a request for service at its DREQ input by switching it to logic 1.
In response to the active DMA request, the DMA controller switches the
hold request (HRQ) output to logic 1.
HLDA of the 8088 is applied to the HLDA input of the 82C37A and signals
that the system bus is now available for use by the DMA controller.
82C37A tells the requesting peripheral device that it is ready by outputting
a DMA-acknowledge (DACK) signal
During DMA bus cycles, the DMA controller not the MPU, drives the
system bus
Atl the beginning of all DMA bus cycles, a 16-bit address is output on
lines A0 through A7 and DB0 through DB7.
The upper 8 bits of the address available on the data bus lines, appear
at the same time that address strobe (ADSTB) becomes active
ADSTB is intended to be used to strobe the most significant byte of the
address into an external address latch.
This 16-bit address gives the 82C37A the ability to directly address
up to 64Kbytes of storage locations
The address enable (AEN) output signal is active during the complete
DMA bus cycle and can be used to both enable the address latch and
disable other devices connected to the bus
The 82C37A performs both the memory-to-I/O and l/O-to-memory DMA
bus cycles in just four clock periods, while performs memory-to-memory
DMA bus Cycles in eight clock periods
The READY input is used to accommodates low memory or I/O devices
Internal Architecture of the 82C37A
Internal Registers of the 82C37A
Timing and control: generates the timing and control signals needed by
the external bus interface, it accepts as inputs the READY and CS
signals and produces output signals such as ADSTB and AEN.
Priority encoder and rotating priority logic: recognizes one of two
priority schemes that can be selected by the 82C37A under software
control: fixed priority and rotating priority.
The command control: decodes the register commands applied to
the 82C37 A through the microprocessor interface.
12 different types
of registers
Accessing the
registers of the
82C37A
Each DMA channel has two address registers: the base address register
and the current address register, The base address register holds the
starting address for the DMA operation, and the current address register
contains the address of the next storage location to be accessed.
To load a new 16-bit address into the base register, we must write two
separate bytes, one after the other, to the address of the register. The
82C31A has an internal flip-flop called the first/last flip-flop. This flip-flop
identifies which byte of the address is being written into the register.
Example: to write the address 123416 in to the base address register and
This routine assumes that the internal flip-flop was initially set to 0
The 82C37A also has two word count registers for each of its DMA channels:
the base count register and the current count register.
These registers are 16 bits in length, and identifies their address as 116
relative to the base address DMA for channel 0.
Actually, the number of bytes transferred is always one more than the value
programmed into this register. This is because the end of a DMA cycle is
detected by the rollover of the current word count from 000016 to FFFF16.
Example: to program a count of 0FFFI6 into the base and current count
registers for channel 1 of a DMA controller located at address DMA (where
DMA ≤ F0H), the following instructions can be executed:
Again, we have assumed that the internal flip-flop was initially cleared
Command Register
The 8 bits in this register are used to control operating modes that apply to all
channels of the DMA controller.
Command Register
Mode Registers
There is a separate mode register for each of the four DMA channels, each is
eight bits in length. Their bits are used to select various operational features
for the individual DMA channels.
Mode Registers
The two least significant bits are a 2-bit code, which identifies the channel
to which the mode command byte applied.
The two most significant bits of the mode register select one of four possible
modes of DMA operation for the channel:
Demand mode: bytes are continuously transferred as long as the DREQ
signal remains active and the terminal count (TC) is not reached.
Single mode: used when it is necessary to not lock the microprocessor off
the bus for the complete duration of the DMA operation.
Block mode: DREQ can be released at any time after the DMA cycle
begins, and the block transfer will still run to completion.
Cascade mode: used when more than one 8237 is present in a system.
Request Register
When the request bit for a channel is set. DMA operation is started, and when
reset. The DMA cycle is stopped. Any channel used for software-initiated DMA
must be programmed for block-transfer mode of operation.
Mask Register
When a mask bit is set, the DREQ input for the corresponding channel is
disabled. Therefore, hardware requests to the channel are ignored.
relative register address F16
relative register address A16.
At system initialization, it is a common practice to clear the mask register.
Thus, we see that a special command is provided to perform this operation.
Executing an output cycle to the register with relative address E16 clears the
mask register.
Status Register
Contains information about the operating state of the four DMA channels.
The 8088 can read the contents of the status register through software. This
is done by initiating an input bus cycle for register address 816 relative to the
base address for the 82C37A.
Temporary Register
during memory-to memory DMA transfers, the data read from the
source address are held in a register known as the temporary register
and then a write cycle is initiated to write the data to the destination
address.
At the completion of the DMA cycle, this register contains the last byte
that was transferred. The value in this register can be read by the
microprocessor.
DMA Interface for the 8088-Based Microcomputer Using the
82C37A
Both the 8088 MPU and the 82C37A DMA controller drive the same three
system buses: address bus, data bus. and control bus.
During the DMA operation, the 82C37A generates alI of the bus signals that
are needed to access I/O devices and the memory. It also generates the
AEN signal, which is used to disable the microprocessor's connection to the
system bus.
AEN does this by disabling the control bus decoder and the latches for the
address bus. The microprocessor's connection to the data bus is also
disabled in response to the hold request received on its HOLD input.
Remember that logic 1 at HOLD puts the data bus lines in the high-Z state,
Thus, during a DMA operation, the 82C37A is in complete control of the
address bus, control bus, and data bus.
10.10 SERIAL COMMUNICATION INTERFACE
Serial Communication Port: I/O interface, used to connect peripheral units,
such as CRT terminals, modems, and printers, to a microcomputer.
It permits data to be transferred between two units using just two data lines
One line is used for transmitting data and the other for receiving data.
Types of serial data communications.
Synchronous communications.
Asynchronous communications.
Synchronous communications
The receiver and transmitter sections of the two pieces of equipment communicating
with each other must run synchronously.
To initiate synchronous transmission, the transmitter first sends out synchronization
characters to the receiver.
The receiver reads the synchronization bit pattern and compares it to a known sync
pattern. Once they are identified as being the same, the receiver begins to read
character data off the data line.
Transfer of data continues until the complete
block of data is received.
If large blocks of data are being sent, the
synchronization characters may be
periodically resent to assure that
synchronization is maintained.
Used in applications where
high speed data transfer is
required.
Asynchronous communications
The asynchronous method of communication eliminates the need for the Clock signal.
The simplest form of an asynchronous communication interface could consist of a
Receive data, Transmit data, and Signal common communication line.
The data to be transmitted are sent out one character at a time, and at the receiver
examining synchronization bits that are included at the beginning and end of each
character performs end of the communication line synchronization.
The synchronization bit at the beginning of the
character is called the Start bit, and that at the
end of the character the stop bit.
Depending on the communications
scheme, 1, 1.5, or 2 stop bits can be used.
The bits of the character are embedded
between the start and stop bits.
7-bit ASCII can be used and parity
added as an eighth bit for higher
reliability in transmission.
Simplex, Half-Duplex, and Full-Duplex Communication Links
Baud Rate and the Baud-Rate Generator
Baud rate: The rate at which data transfers take place over the receive
and transmit lines.
By baud rate we mean the number of bits of data transferred per second.
some of the common data transfer rates
300 bps
1200 bps
9600 bps
Baud rate is set by a part of the serial communication interface called the
Baud rate generator.
The baud rate at which data are transferred determines the bit time, that
is, the amount of time each bit of data is on the communication line. At
300 baud rate, the bit time is found to be 3.33 ms.
The RS-232C Interface
is a standard hardware interface for implementing asynchronous serial data
communication ports on devices such as printer,CRT terminal, keyboards, and
modem.
Electronic Industries Association (EIA) defines the pin definitions and
electrical characteristics of this interfaces.
In large systems it is common to have the microcomputer part of the system
in a separate room from the terminals and printers.
This leads us to the main advantage of using a serial interface to connect
peripherals to a microcomputer, which is that as few as three signal lines
can be used to connect the peripheral to the MPU. a receive-data lin e, a
transmit-data line. and signal common.
This result in a large saving in wiring costs, and the small number of lines
that need to be put in place also leads to higher reliability.
The RS-232C Interface
Data Terminal Equipment (DTE) & Data Communications Equipment (DCE)
How the signals of the RS-232C interface are used in a device depends on whether it is
configured as DTE or DCE.
The direction for signals in a DTE and a DCE device are reversed.
That is, signal Lines that are outputs on a DTE device are inputs on a DCE
and vice versa.
For instance, if pin 2 on a DTE is an output, it connects directly to pin 2
on the DCE, which acts as an input.
when both devices are configured as DTEs, the data transmitted by
one is received by the other and vice versa.
Cont.
Cont.
The control pins are provided to set up a handshake sequence for initiating
communication between serial devices, like request to send (RTS).
In many systems only three signals TxD, RxD. and common are used to
provide serial communication. In such a set up no handshakes sequences
used to initiate communication.
The RS-232C interface is specified to operate correctly over a distance
of up to 100 feet
To satisfy this distances specification, bus driver is used on the transmit
line and a bus receiver is used on the receive line.
These buffers do both the voltage level translation needed to convert the
TTL compatible signals to the mark (logic 1) and space (logic 0) voltage
levels defined for the RS-232C interface
10.11 PROGMMMABLE COMMUNICATION INTERFACE CONTROLLERS
The functions of RS-232 are normally implemented with a programmable
communication controller known as Universal synchronous/asynchronous
receiver transmitter (USART).
The programmability of the USART provides for a very flexible asynchronous
communication interface.
Typically. it contains a full-duplex receiver and transmitter which can be
configured through software.
Character lengths between 5 and 8 bits.
even or odd parity
with 1, 1.5, or 2 stop bits
has the ability to automatically check characters during data reception to
detect the occurrence of parity, framing, and overrun errors.
8251A USART
Includes four key sections:
the bus interface section, which consists of the data bus buffer
and read/write control logic blocks.
the transmit section, which consists of the transmit buffer and
transmit control block.
the receive section, which consists of the receive buffer and
receive control block.
the modem-control section.
The receiver section
Is responsible for reading the serial bit stream of data at the RxD (receive data)
input and converting it to parallel form.
When a mark voltage level is detected on this line, indicating a start bit, the
receiver enables a counter
As the counter increments to a value equal to one-half a bit time, the logic
level at the RxD line is sampled again.
If it is still at the mark level, a valid start pulse has been detected.
Then RxD is examined every time the counter increments through another bit
time.
This continues until a complete character is assembled and the stop bit is
read.
After this, the complete character is transferred into the receive-data register.
During reception of a character
the receiver automatically checks the character data for parity, framing, or
overrun errors.
If one of these conditions occurs, it is flagged by setting a bit in the status
register.
Then the RxRDy (receiver ready) output is switched to the 1 logic level.
This signal is sent to the microprocessor to tell it that a character is available
and should be read from the receive-data register.
RxRDy is automatically reset to logic 0 when the MPU reads the contents of
the receive_data register.
Through software, the 8251A can be set up to internally divide the
Clock signal input at Rxc by 1, 16, or 64 to obtain the desired baud rate.
The transmitter section
does the opposite of the receiver section.
It receives parallel character data from the MPU over the data bus.
The character is then automatically framed with the start bit, appropriate
parity bit and the correct number of stop bits and put into the transmit-data
buffer register.
Then, the serial output on the TxD line will be sent.
The TxRDY output switches to logic 1, This signal can be returned to the MPU
to tell it that another character should be output to the transmitter section.
In most applications, the transmitter receiver operate on the same baud
rate. Therefore, the same baud-rate generator supplies both Rxc and Txc.
Receiver and transmitter driven at the same baud rate.
Configuration of 8251A
8251 can be configured for various modes of operation through software.
It has three internal control registers:
mode-control register
command register
status register.
Mode instruction
Format.
configuration for
asynchronous
communications
Command
instruction
Format.
For serial
interface
flags for the receiver
Status register
Initialization of 8251A
Answer = 5E
assume
EXAMPLE 10.31
Reset
X
8250/16450 UART
These devices are newer than the 8251A UART and implement a
more versatile serial I/O operation. For instance, they have a builtin programmable baud rate generator double buffering on
communication data registers, and enhanced status and interrupt
signaling.
KEYBOARD AND DISPLAY INTERFACE
Debouncing: is achieved by resampling the column lines a second
time, about 10 ms later.
Two-key lock: With this method, the occurrence of a second key
during the debounces can causes both keys to be locked out, and
neither is accepted by the microcomputer.
N-key rollover: In this case. more than one key can be depressed at a
time and be accepted by the microcomputer.
82C54
PROGRAMMABLE
INTERVAL TIMER
82C54 PROGRAMMABLE INTERVAL TIMER
Block Diagram of 82C54
Signals of 82C54
Pulses applied to the clock input are used to decrement the
certain counter
The gate input is used to enable or disable the certain counter.
The counter produces either a clock or a pulse at the OUT pin
depending on the mode of operation selected.
The 82C54 is rated for a maximum clock frequency of 10 MHz
Architecture f the 82C54
Architecture f the 82C54
82C54 consists of:
Data bus buffer.
read/write logic.
Control word register: The control word register section actually contains
three 8-bit registers used to configure the
operation of counters 0, 1, and 2
three counters.
Control word format
Accessing the registers of the 82C54
Solution
How the contents of a counter register could be read?
One approach is simply to read the contents of the corresponding
register with an input instruction.
To ensure that a valid count is read out of a certain count register,
the counter must be inhibited before the read operation takes
place.
The easiest way to do this is to switch the GATE input to logic 0
before performing the read operation.
The count read as two separate bytes, low bytes followed by the
high byte.
The contents of the count registers can also be read without first
inhibiting the counter. That is, the count can be read on the fly.
To do this in software, a command must first be issued to the
mode register to capture the current value of the counter into a
temporary internal storage register.
Setting bits D5 and D4 of the mode byte to 00 specifies the latch
mode of operation, which is works just like before. .
read - back mode
Permit the programmer to capture the current count values and
status information of all three counters with a single command.
to capture the values in all three counters, The correct command must be
written into the control word register of the 82C54.
When both count and status information is captured with a read back
command, two read counter commands are required to return the information
to the MPU. During the first read operation, the value of the count is read, and
the status information is transferred during the second read operation.
Examples for Read-Back command
Status information
The transition in the output occurs after n+1 clock pulses.
retriggerable one-shot
The duration of the pulse equals the value loaded in the register (n).
divide-by- N counter
The period of the symmetrical square wave at the output equals
the number loaded into the counter multiplied by the period of the
input clock.
If an odd number (N) is loaded into the counter instead of an even
number, the time for which the output is high depends on (N+1)/2,
and the time for which the output is low depends on (N-l)/2.