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MOTOROLA 68HC08 INTRODUCTION AND SYSTEM OVERVIEW

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CONTENTS

68HC08 Micro Controller Family Evolution CSIC Design Philosophy CPU08 Overview 68HC708 Architecture Overview Module Preview 68HC08 Technical Support

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Motorola's 6800 Family Evolution

32- & RISC 16-Bit

Architecture

8-Bit 6800 68000 68020 68HC11 60 Versions MPC600 MPC500 68300 15 Versions Hardware Compatibility 68HC16 12 Versions Software Compatibility 68HC12 2 versions Most Powerful 68HC08 15 Versions 68HC05 180 Versions Least Expensive

Time Motorol a

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Design Goals for 8-bit Microcontrollers

Broad product offering for tiered performance application needs Higher performance, cost sensitive Easy migration path for existing 68HC05 users Ability to meet new customer requirements quickly Low voltage capable High quality, cost effective manufacturing capabilities Documentation and development support

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Motorola's Solution: The 68HC08 CPU

HC05 object code compatible Architecturally enhanced 68HC05 CPU 5x average performance increase CSIC's first unified design rules (UDR) core New module based CSIC design/test methodology CPU architecture extensibility

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68HC08 Modular CSIC Solution

Clock Ge ne ration M odule Syste m Inte gration M odule 68HC08 CPU Internal Bus (IBUS) Time r M odule Pe riphe ral M odule RAM M e mory ROM Type M e mory Pe riphe ral M odule Pe riphe ral M odule Modularity Requirements

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Standard internal bus definition Standard module heights Standard module definition Reduced Die Size (Cost-effectiveness)

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Individual modules hand packed to take up less silicon

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No excessive glue logic

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Building a CSIC from a Module Library

CSIC LIBRARY CPU SIM DMA ADX EXT BUS TIM CPM PLL RTC OSC OSD SCI PWM LCD SPI A/D PTA PTB PTC PTD MEM GEN CPM – CUSTOMER PROPRIETARY MODULE

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MC68HC08 68HC08 CPU

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HC05 Single Chip Operation (except for 68HC05C0) No Direct Control of the Stack Pointer One 8-Bit Index Register One 8-Bit Accumulator 8-Bit Math with MUL Instruction IDR Process (4Mhz bus)

68HCxx 8-BIT CPU Cores Major Differences

HC08 Single Chip and Expanded Modes Direct Control of Stack Pointer via PUSH/PULL Instructions One 16-Bit Index Register One 8-Bit Accumulator 8-Bit Math with MUL and DIV Instructions UDR Process (8 Mhz bus) HC11 Single Chip and Expanded Modes Direct Control of Stack Pointer via PUSH/PULL Instructions Two 16-Bit Index Register Two 8-Bit Accumulator or One 16-Bit Accumulator 16-Bit Math with MUL and DIV instructions IDR P Process (4 Mhz bus)

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Let's take a closer look at the CPU

LVI Module COP Module Clock Generation Module System Integration Module IRQ Module RESET Module 68HC08 CPU Internal Bus (IBUS) DMA Module BREAK Module RAM Memory ROM Type Memory Timer Module Peripheral Module Peripheral Module Peripheral Module Peripheral Module

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68HC08 CPU Design Accomplishments

Increased Bus Speed of 8Mhz at 5V Sub-micron UDR process Improved Instruction Set and Addressing Modes Opcode Look-Ahead Instruction Prefetch Optional Modular Extensions

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DMA module reduces interrupt overhead

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Address extension module increases address bus to 24 bits for > 64K data/program space

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68HC08 Instruction Preview

Data Movement

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Load, Store, Move, Stack Arithmetic

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Add, Sub, Mul, Div Logical

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And, Or, Eor Data and Bit Manipulation

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Shifts, Rotates, Bit Test Program Control

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Branch, Subroutine Binary Coded Decimal Looping Constructs Special High Level Language Support

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68HC08 Addressing Preview

Inherent Immediate Direct Extended Indexed

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8 and 16 bit offset Stack Pointer Post Increment Relative Memory to Memory

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Direct Indexed

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68HC08 Instruction/Addressing Summary

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Stack Manipulation (48 new instructions)

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Directly push/pull any register & add immediate to stack Stack relative addressing mode

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Temporary variables on the stack can be manipulated directly, without loading them into the accumulator Index Extension Register (7 new instructions)

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Allows use of full 16-bit index register (H:X) Memory to Memory Move (4 new instructions) Looping Constructs (12 new instructions)

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Decrement and Branch

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Compare and Branch Arithmetic Enhancements (1 new instruction)

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Faster multiply (5 clks vs 11) Divide (16/8) BCD Support (2 new instructions)

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Decimal adjust accumulator and nibble swap accumulator C Compiler Support (4 new instructions)

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Conditional branch with signed operands

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68HC08 Flagship MC68HC708XL36

Clock Generation Module Serial Communications Interface System Integration Module Serial Peripheral Interface LVI IRQ COP BREAK RESET Internal Bus (IBUS) 68HC08 CPU Random Access Memory Electronically Programmable ROM Timer Interface Module Direct Memory Access Module Monitor ROM Architecturally Enhanced 8-bit CPU 1Kbyte RAM and 36Kbytes EPROM 240 Bytes Monitor ROM System Control and Protection Modules (SIM) Direct Memory Access Module (DMA) General Purpose Timing Interface Module (TIM) Serial Communication Modules (SCI and SPI)

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CPU SYSTEM MODULES

³ Low Voltage Inhibit (LVI) ³ ³ ³ Computer Operating Properly (COP) Break Module External Interrupt Module (IRQ) ³ System Integration Module (SIM) • Manages System Protection – Reset on illegal address and illegal opcode – Optional reset on LVI and COP • Manages Interrupts with up to 128 separate vectors • Bus Clock Generation for CPU and most Peripherals

CLOCK GENERATION MODULE(CGM)

³ Provides clock inputs into SIM Module and SCI Baud Generator ³ Crystal Oscillator circuit and phase locked loop circuit • Avoids the cost and noise of high frequency crystals ³ Programmable bus frequency • Integer multiples (1 to 15) of crystal frequency ÷ 4

TIMING INTERFACE MODULE (TIM)

³ Modular architecture ³ 68HC05C4 timer compatible channels • Input capture, Output Compare, PWM ³ Counter may be free-running or modulo up-counter • Optionally toggle any channel output on overflow ³ Timer interrupts can select CPU or DMA servicing

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DIRECT MEMORY ACCESS (DMA)

³ DMA can be used to reduce CPU overhead of processing normal data movement interrupts ³ Using DMA to service peripherals instead of CPU interrupts can dramatically reduce interrupt overhead • A byte transfer takes only two clocks (4 MByte/sec peak) • CPU processing continues after the DMA transfer as if nothing happened ³ Allows transfers between any two CPU addressable locations ³ ³ Expandable architecture up to seven channels Block transfer capability of up to 256 bytes ³ ³ ³ Programmable bus bandwidth utilization of 25% to 100% Optional CPU interrupt upon completion data block transfer Optional enable for DMA operation during low power wait

SERIAL PERIPHERAL INTERFACE (SPI)

³ Compatible with HC05 SPI but with enhancements: • Separate receive and transmit buffers avoid write collisions • Programmable wired-or mode • DMA can service normal data movement SPI interrupts

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SERIAL COMMUNICATIONS INTERFACE (SCI)

³ Compatible with HC05 SCI but with enhancements: • Optional HW parity • Two idle line receiver wakeup methods • Additional interrupt vectors and interrupt enables • Loop mode for diagnostics/test • DMA can service normal data movement SCI interrupts

MEMORY MODULES

³ 1 KByte fully static 8-bit RAM ³ 36 KBytes of 8-bit user-programmable ROM • Windowed packages available for UV erasure • One-time programmable non-windowed packages • EPROM security mode

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New Module Development

Modules currently in design or targeted2, 6, & 8 Channel Programmable Timers

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I Dedicated 8-bit & 16-bit Pulse Width Modulation Analog/Digital Converter (8-bit and 10-bit) External Bus Interface Address Extension Comparators RAM EPROM ROM EEPROM 2 C LCD Customer Specific OSD - On Screen Display

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68HC08 Summary

Architecture is an extension of the world's leading 8-bit microcontroller family - 68HC05 Offers a high performance, cost-effective migration for existing HC05 applications Modular design and test methodology gives Motorola ability to meet customer new product requirements with dramatically lower cycle time Supported by a portfolio of development tools to program, evaluate and design applications

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