ECE369: Fundamentals of Computer Architecture

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Transcript ECE369: Fundamentals of Computer Architecture

ECE 369 Chapter 4

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addi $29, $29, 16 Assume register $29 initially contains the number 129.

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addi $29, $29, 16 Assume register $29 initially contains the number 129.

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What happens at stuck at 0 for….?

RegWrite R-format instructions, in addition to lw: will not be able to write ECE369 their results to the register file.

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What happens at stuck at 0 for….?

ALUop1 All R-format instructions How about add or sub? ECE369 5

What happens at stuck at 0 for….?

ALUop0 Beq instruction will not work because the ALU will perform ECE369 addition instead of subtraction 6

What happens at stuck at 1 for….?

RegWrite Sw (beq) will overwrite a random register with either the store ECE369

New inruction (l_inc)= lw $rs, addi $rt, ($rt) $rt,1 You can modify the datapath

: a) Introduce new module(s) b) Introduce input(s)/output(s) to existing modules c) Add new control signal(s)

Reg Dest ALU Src MEMto Reg Reg Write Mem Read Mem Write

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Branch ALUop1 ALUop0

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New instruction (l_inc)= lw $rs, addi $rt, ($rt) $rt,1

Auto incrementer unit Second write port (WriteData2) Write2 control signal Feed Inst[25-21] to second write port Write2 controls this write

Reg Dest 0 ALU Src 1 MEMto Reg 1 Reg Write 1 Mem Read 1 Mem Write Branch 0 ALU Op1,op0 00 Write2 1

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Modify single cycle to implement Jump Register

(Jr $rs) = PC<-$rs

Reg Dest ALU Src MEMto Reg Reg Write Mem Read Mem Write

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Branch ALU Op1,op0

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Modify single cycle to implement Jump Register

(Jr $rs) = PC<-$rs

Reg Dest x ALU Src x MEMto Reg x Reg Write 0 Mem Read x Mem Write Branch 0 ALU Op1,op0 x Jump Reg 1

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bmez $rt, $rs, imm16

RegWrite reads the value of memory in address (R[$rs] + R[$rt]), compares it to zero and if zero then branches to the zero extended immediate, otherwise it goes on to the next instruction.

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sw+ is a “store word, with post increment” M[R[rs]] = R[rt] R[rs] = R[rs] + imm

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Modify the datapath to handle: lw rt, rs sw rt, rs # R[rt] = M[R[rs]] # M[R[rs]] = R[rt] ECE369 16

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mov rs, rd # R[rd] = R[rs];

Instr

mov

ALUsrc1 ALUsrc2 ALUsrc3 ALUop1 ALUop2 MemRead MemWrite RegWrite ECE369 19

a_new rd, rs, rt, imm # Memory[R[rs]]= (R[rs] | imm) + R[rt]

Instr

a_new

ALUsrc1 ALUsrc2 ALUsrc3 ALUop1 ALUop2 MemRead MemWrite RegWrite ECE369 20

b_new rd,rs,rt,imm # R[rd]=R[rs]+Imm+ Memory[R[rs]]

Instr

b_new

ALUsrc1 ALUsrc2 ALUsrc3 ALUop1 ALUop2 MemRead MemWrite RegWrite ECE369 21

Timing Analysis

Instruction Func. Unit Instruction Memory (Read) Data Memory (Read/Write) Add ALU Register (Read) Register (Write) Latency 2ns 5ns 1ns 3ns 2ns 4ns Given the latencies above, what is the

minimum cycle time

for this processor based on the addi_lw , mov, a_new and b_new instructions? Show your work to get credit.

Instruction Memory Add Potential resources used by an instruction Register Read Register Write Data Memory Read Data Memory Write ALU1 ALU2 mov a_new b_new ECE369 Total 22

Mov: Rt=0, imm=0 a_new:

ALU2 output needs to be connected to write data part through a mux

Instr

mov x a_new b_new 1

ALUsrc1 ALUsrc2 ALUsrc3 ALUop1 ALUop2 MemRead MemWrite RegWrite

1 1 add add 0 0 1 0 0 add

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add 1 0 1

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Func. Unit Instruction Memory (Read) Data Memory (Read/Write) Add ALU Register (Read) Register (Write) Latency 2ns 5ns 1ns 3ns 2ns 4ns Given the latencies what is the

minimum cycle time

for this processor based on the addi_lw , mov, a_new and b_new instructions? Show your work to get credit.

Instruction addi_lw mov a_new b_new

2 2 2 2

Instruction Memory Add Potential resources used by an instruction Register Register Data Data Read Write Memory Read Memory Write

1 1 2 2 4 4 0 0 5 0 1 1 2 2 0 4 0 0 5 5

ALU1

3 3 3 3

ALU2

3 3 3 3

Total

14 14 15 16

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