Transcript Memory Testing and Pattern Introduction

Memory Testing and
Pattern Introduction
TM
TM
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
Contents
• Brief Introduction
• Memory Classification and Application
• How to Test Memory IC
• Pattern Introduction
• Scramble
TM
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
Memory IC Testing
• For storage media (memory):
not magnetic tape, not hard/floppy disk, not brain
• For silicon process:
not WAT test, not reliability test,
not physical failure analysis
• For IC testing:
not logic (ASIC, CPU, FPGA, LCD driver, …)
not mix-signal (ADC, DAC, USB, …)
• For test program:
not timing, not pin format, not hardware configuration
not command to generate report, not user interface
• We focus on:
electrical failure analysis, (memory IC) function test, test pattern
TM
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
Memory Classification
• Volatile memory: data will lose after power off
SRAM (static random access memory):
Low Power (or Low Voltage) SRAM / High Speed SRAM
DRAM (dynamic RAM, need refresh):
Synchronous DRAM / Double Data Rate (DDR) SDRAM
FCRAM (FJ, Fast Cycle RAM): DRAM cell with SRAM peripheral
• Non volatile memory: data still keep after power off
ROM (read only memory) / PROM (programmable ROM)
EPROM (Erasable PROM) / EEPROM (Electrical EPROM)
Flash
• Embedded Memory :
some of above memories are merged with some logical purpose
circuit on a chip
TM
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
Memory Application
• LP-SRAM: mobile phone
• HS-SRAM: cache memory
• DRAM: phase out
• SDRAM / DDR SDRAM: mother board / graphic card
• ROM / PROM / EPROM: game machine / BIOS
• EEPROM / Flash: smart card / voice recorder
• FCRAM(FJ): mobile phone
TM
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
Special Testing Feature
• SRAM: typical memory function (Write and Read)
• DRAM: row and column address are multiplexed, need refresh
• SDRAM: need one synchronous clock, pipe-line (burst) concept
• DDR SDRAM: one cycle two data, write latency, DLL on/off
• FCRAM: need some test mode to access the DRAM cell
• ROM: need SOM (source only memory) board of tester, read only
• EEPROM / Flash: read / program / erase all / page mode
address and data are multiplexed, BUSY signal
• Embedded Memory: in general, several hundreds pins, so we need
customer provide more detailed or confidential document about
the memory-related, only around fifty pins information to run a
specified sequence to enter the direct access mode
TM
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
From the PC BIOS’s View
• For the PC with 256M bytes SDRAM (the simplest way,
mail box)
write all 0x00, read all 0x00
be visited 2 times
write all 0xFF, read all 0xFF
be visited 2 times
write all 0x55, read all 0x55
be visited 2 times
write random, read random
be visited 2 times, total 8 times
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
:
:
:
:
…..
…..
L L L L L L L L L L L L L L L L
L L L L L L L L L L L L L L L L
:
:
:
:
…..
…..
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
:
:
:
:
…..
…..
H H H H H H H H H H H H H H H H
H H H H H H H H H H H H H H H H
:
:
:
:
…..
…..
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
:
:
:
:
…..
…..
L H L H L H L H L H L H L H L H
L H L H L H L H L H L H L H L H
:
:
:
:
…..
…..
write random data 1
write random data n
:
:
TM
write random data 2
write random data n+1
:
:
…..
…..
read random data 1
read random data n
:
:
read random data 2
read random data n+1
:
:
…..
…..
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
What We Say the “Testing”
• For the 16Mx8 bits SDRAM
1. In general, when we are debugging or creating a pattern,
we always just consider one DQ only.
2. In order to get good fault coverage and measure almost all the
device feature listed on data sheet, a test program will access
each bit more than several hundreds times, not only few times
DQ8 0 0 0
…..
DQ7 0 0 0
…..
DQ6 0 0 0
…..
0
DQ5 0 0 0
…..
0 0
DQ4 0 0 0
…..
0 0 0
DQ3 0 0 0
…..
0 0 0 :
DQ2 0 0 0
…..
0 0 0 : :
DQ1 0 0 0
…..
0 0 0 : : :
0 0 0
…..
0 0 : : : 0
1024 : : : :
: : : : 0
bit : : :
:
: : : 0
lines : : :
….. : : : 0
0 0 0
…..
0 0
16384 word lines
TM
0 0
0 0 0
0 0 :
0 : :
: : :
: : 0
: 0
0
DQ1 to DQ8 are accessed in the
same time for every address
DQn 0 0 0
…..
0 0 0
…..
1024 : : : :
bit : : :
:
lines : : :
….. :
0 0 0
…..
16384 word lines
0 0
0 0
: :
: :
: :
0 0
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
Elements of Pattern
• the most important is address and data:
simple
memory
1 2 3
4 5 6
TM
simple pattern:
command W W W W W W
address
1 2 3 4 5 6
data
0 0 0 0 0 0
R R R R R R
1 2 3 4 5 6
0 0 0 0 0 0
command
address
data
R R R R R R
1 2 3 4 5 6
1 1 1 1 1 1
W W W W W W
1 2 3 4 5 6
1 1 1 1 1 1
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
Pattern Classification
• For written data (background data):
solid 0/1, row bar, column bar, checker board,
diagonal, DQ switch, RWI (repeat with invert)
• For cell visiting sequence (address changing):
write-verify, scan X/Y, march4n, march6n,
inverse, address complement, RWI
• Take too long time and less use
galloping, butter-fly, shift diagonal --- n^2
• For DRAM special:
disturb, Long RAS
TM
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
Background Data
• In testing world:
0
0
0
0
solid 0
row bar
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
solid 1
1
1
1
1
X is ROW is WL (word line),
Y is COLUMN is BL (bit line)
1
1
1
1
1
1
1
1
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1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
row bar RWI
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
column bar
2 column bar
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
column bar RWI diagonal
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
checker board
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
checker board RWI
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
DQ Switch (polarity)
solid 0 with 0x00
DQ8 0 0 0 …..
DQ7 0 0 0 ….. 0
DQ6 0 0 0 ….. 0 0
DQ5 0 0 0 ….. 0 0 0
DQ4 0 0 0 ….. 0 0 0 :
DQ3 0 0 0 ….. 0 0 0 : :
DQ2 0 0 0 ….. 0 0 0 : : :
DQ1 0 0 0 ….. 0 0 0 : : : 0
0 0 0 ….. 0 0 : : : 0
: : : :
: : : : 0
: : :
:
: : : 0
: : : ….. : : : 0
0 0 0 ….. 0 0
TM
0
0
0
:
:
:
0
0
0
:
:
:
0
checker board with 0xAA
DQ8 1 0 1 …..
DQ7 0 1 0 …..
DQ6 1 0 1 ….. 1
DQ5 0 1 0 ….. 0 1
DQ4 1 0 1 ….. 1 0 0
DQ3 0 1 0 ….. 0 1 1 :
DQ2 1 0 1 ….. 1 0 0 : :
DQ1 0 1 0 ….. 0 1 1 : : :
1 0 1 ….. 1 0 : : : 0
: : : :
: : : : 1
: : :
:
: : : 0
0
: : : ….. : : : 1
1
1 0 1 ….. 1 0
0
no tester (ALPG) can do this with 0x69
DQ8 0 0 0 ….. 0 0
0
DQ7 0 1 0 ….. 0 1 1
0
DQ6 0 1 0 ….. 0 1 1 :
1
DQ5 0 0 0 ….. 0 0 1 : :
:
DQ4 0 1 0 ….. 0 1 1 : : :
:
1
DQ3 0 0 0 ….. 0 0 1 : : : 1 col bar
:
0
DQ2 0 0 0 ….. 0 0 1 : : : 1 row bar
1
1
DQ1 0 1 0 ….. 0 1 1 : : : 1 row bar
0
0 1 0 ….. 0 1 : : : 1 col bar
1
: : : :
: : : : 1 row bar
: : :
:
: : : 1 col bar
: : : ….. : : : 1 col bar
0 1 0 ….. 0 1 row bar
1
1
0
:
:
:
0
0
1
:
:
:
1
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
X-Fast vs. Y-Fast
simple
memory
1 2 3
4 5 6
TM
X-Fast:
command
address
data
W W W W W W
1 2 3 4 5 6
1 1 1 1 1 1
Y-Fast:
command
address
data
W W W W W W
1 4 2 5 3 6
1 1 1 1 1 1
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
Write Solid1 and RWI
simple
memory
1 2 3
4 5 6
TM
write solid1:
command W W W W W W
address
1 2 3 4 5 6
data
1 1 1 1 1 1
write solid1 and repeat with invert:
command W W W W W W W W W W W W
address
1 2 3 4 5 6 1 2 3 4 5 6
data
1 1 1 1 1 1 0 0 0 0 0 0
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
Scan vs. Write Verify
simple
memory
1 2 3
4 5 6
TM
Scan-X (write-read):
command W W W W W W R R R R R R
address
1 2 3 4 5 6 1 2 3 4 5 6
data
0 0 0 0 0 0 0 0 0 0 0 0
Write Verify:
command W R W R W R W R W R W R
address
1 1 2 2 3 3 4 4 5 5 6 6
data
0 0 0 0 0 0 0 0 0 0 0 0
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
Scan to March-4n
simple
memory
1 2 3
4 5 6
TM
MarchX-4n:
command W W W W W W R W R W R W
address
1 2 3 4 5 6 1 1 2 2 3 3
data
0 0 0 0 0 0 0 1 0 1 0 1
then:
command
address
data
R W R W R W R R R R R R
4 4 5 5 6 6 1 2 3 4 5 6
0 1 0 1 0 1 1 1 1 1 1 1
Scan-X:
command
address
data
W W W W W W R R R R R R
1 2 3 4 5 6 1 2 3 4 5 6
0 0 0 0 0 0 0 0 0 0 0 0
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
March-6n
simple
memory
1 2 3
4 5 6
TM
MarchX-6n:
command W W W W W W R W R W R W
address
1 2 3 4 5 6 1 1 2 2 3 3
data
0 0 0 0 0 0 0 1 0 1 0 1
then:
command
address
data
R W R W R W R W R W R W
4 4 5 5 6 6 1 1 2 2 3 3
0 1 0 1 0 1 1 0 1 0 1 0
then:
command
address
data
R W R W R W R R R R R R
4 4 5 5 6 6 1 2 3 4 5 6
1 0 1 0 1 0 0 0 0 0 0 0
This document is strictly confidential and proprietary of SMIC. It must not be copied or used for any
purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
Data / Address Scramble
• Data scramble: only for DRAM, caused by Bit Line and /BL
• Address scramble: in general, DRAM simple, SRAM complex
TM
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purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.
Display Scramble
• Display scramble: whole chip address decoding rule
or chip architecture and DQ sequence
• describe the relationship between the electrical address
and topological (physical) address
TM
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purpose other than for reference only, and SMIC shall not be liable or responsible for any reliance.