Transcript Software Defined Radio Introduction

Software Defined Radio
RF (Radio Frequency)
성균관대학교
정보통신공학부
조준동
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Multiple Access Rf for SDR
Smart Antenna
MIMO Channel/
S-T Processing
Diversity
ITS
Micro Cell
Multi-mode Terminal Macro Cell
by Software Radio
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Communications in RF
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다중모드 광대역 소형화
SDR RF 기술
•Homodyne 설계 기술 (zero-IF 기술)
•GSM2Plus + CDMA + 3GPP + 3GPP2을
모두 수용하는 RF 회로
• ADC: 10W – 5Gsample/w 18-bit
• 광대역 고주파 단일 부품의 구현이
불가능한 부품(예: Amp)들에 대한 multiband 부품 특성 구현을 위한 고주파 회로
기술
•전자파 간섭 및 잡음 제거 기술,
•SDR 용 Smart 안테나
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Smart antenna
Coherent
Multipath
Combination of Array
Processing and SpaceTime Coding
Null
⇒ Capacity
Maximization with
Direct
Diversity and Coding Scatterers Path
Gain without
Bandwidth Expansion
Desired User
Interferer
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Space-Time Processing
• High-Speed Packet Transmission by
M-ary modulation and Multiple Antenna
• Highly Spectral & Spatial Efficient
Transmission
• Optimum Transmit Symbol Set for
Maximizing Channel Capacity
• Efficient Combining of Spatial &
Temporal Diversity
- Layered Space-Time Processing
- Combination of Channel Coding and
Diversity
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Array Antenna types, SDR forum
• Type I
– employ multiple antenna elements
– employ RF combiners such as Butler Matrix.
– a set of multiple feeds to the RF element.
• Type II
– includes the features of type I with one or more
RFs
– RF combiner with beamformer
• Type III
– the most sophisticated antenna system.
– the features of types I and II
along with baseband combiner with beamformer
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SDR 기반의 기지국 스마트 안테나
A. Xavier, J. Razavilar and K. J. R. Liu
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Conceptual RF/IF Types
2nd
IF
R
R
F
T
RF
1st IF
1st IF
RF
RF/IF Type III
R
T
RF
R
T
RF/IF Type IV
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RF
Channel
Selector
Channel
ChannelSelector
Selector Baseband
Processing
Channel
Selector
Channel
Selector
Channel Selector
DAC &
ADC
1st
IF
SDR Forum
DAC & ADC
RF/IF Type II
2nd IF
Channel
Selector
Channel
ChannelSelector
Selector Baseband
Processing
Channel
Selector
Channel
Selector
Channel Selector
DAC & ADC
RF/IF Type I
1st
IF
Channel
Selector
Channel
ChannelSelector
Selector Baseband
Processing
Channel
Selector
Channel
Selector
Channel Selector
DAC & ADC
R
RF
T
RF
Channel
Selector
Channel
ChannelSelector
Selector Baseband
Processing
Channel
Selector
Channel
Selector
Channel Selector
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RF/IF Type I
SDR Forum
•Two stages to frequency translate to
the IF frequency input to the
demodulator/ADC
•Filters used to optimize the bandwidth
and eliminate noise
•Requires accurate and stable Local
Oscillators, and the LNA
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RF/IF Type II
SDR Forum
•One stages to frequency translate to
the IF frequency input to the
demodulator/ADC
•Filters used to optimize the bandwidth
and eliminate noise
•Requires accurate and stable Local
Oscillators, and the LNA
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RF/IF Type III
•RF signal after filtering and amplification is
applied directly to the demodulator/ADC
•LNA on the receive side tends to
limit linearity
RF/IF Type IV
•RF signal is converted directly to digital
format using an ultra high speed
ADC/demodulator to produce the baseband
bit stream
•Digital Channel Selection
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Digital vs. Analog Conversion
Analog LO
Analog
Analog BPF Analog
& Amp
Mixer
RF/IF Type IV
Analog
LPF
LP ADC
Digital LO
Digital
Analog BPF
& Amp
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BP ADC
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Digital
Mixer
Digital
LPF
Mixed Conversion
Analog and Digital
RF 1st IF analog
SDR Forum
Decimation
Control & Filter
Filter Coefficients
2nd IF Digital
Sin{Fc+ Fm-VCOR1}
Digital Complex
Mixer
RFin
=
Sin{Fc+Fm +VCOR1} +Sin{Fc+Fm -VCOR1}
Sin{Fc+Fm}
Low Pass
Filter
Digital
Low Pass
Filter with
Decimation
ADC
I
Polyphase
Interpol.
Filter &
Re-sampler
Q
Rec. IF
Out Analog
=
Sin{VCOT1+Ifin +Fm}
Clk1
VCOR1
Cos
Sin
Re-Sampling
Digital
OSC
Digital Local
OSC
Freq.
Tuning
Receiver
RFout
=
High Pass
Filter
Sin{IFt +Fm +VDOT2} + Sin{VCOT2 - IFt +Fm}
VCOT2
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DAC
Tran IF
Analog
Analog IF Stage
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High
Pass
Digital
Filter
Sin
Digital Local
OSC
Freq.
Tuning
Transmit
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Filter Coefficients
Conventional Heterodyne
Multi-Mode Radio Receiver
2G Cellular
3G Cellular
BT / 802.11
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GSM
1800
UMTS
BT /
802.11
BT /
802.11
0.200MHz BW
5.0-MHz
BW
1.25-MHz
Ch l
1.25-MHz
Ch 2
1.25-MHz
Ch 3
1.0-MHz
BW
LO2
LO3
LO4
LO5
LO6
LO7
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LO1
Low-Pass
10-MHz
Low-Pass
10-MHz
Low-Pass
10-MHz
Low-Pass
10-MHz
Low-Pass
Low-Pass
FDD Mode 1
FDD Mode
2
Legend
GSM
1800
UMTS
Homodyne Multi-Mode
Radio Receiver
GSM
UMTS
UMTS
802.11
802.11
A/D
Converter
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GSM
Programmable
Channel Filter
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LO
I
Q
A Digital Receiver for
Wideband Signal
Channel decoder
Channel
Symbol
Error
Separation Detection Decoder
Source user
Decoder
Distortion caused by the channel
Additive interfering signals
random noise signals
delayed versions of the same signal
I
rn  sn   si ,n  nn
i 0
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Where Sn= signal of interest,
I = interfering signals
nn= random noise component
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Typical Processing For Narrow
Band Channel Selection
Complex
sinusoidal
Filter
Frequency
translation
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Bandwidth
reduction
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Decimator
Sampling rate
reduction
Wideband Channel selection
• Cascade of multiple FIR filter
– bandwidth reduction in several stages
– a lower number operations per output
samples
• Filter bank
– multiple narrowband channels extracted
from the same wideband simultaneously.
– Computing the multiple output at a lower
cost than multiple single channel.
• Cascade integrator comb filter
– cascaded stages of accumulator w/ a
pass band filter using no multiplication
operations
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Zero IF QPSK Demodulation
Analog
Digital
cos(wot)
RF input
= 2GHz)
I (50MS/s)
A/D
RF filter LNA
A/D
chip boundary
Crystal
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Digital
Baseband
Receiver
Q (50MS/s)
sin(wot)
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BWRC’s
Receiver Prototype
Jan Rabaey
I SD
PLL
Q SD
baseband
filters
mixer
LNA
Area = 4 mm2
Noise Figure = 8.5 dB
90 kHz < f < 18 MHz
PLL Phase Noise: -85
dBc/Hz @ 2.5 MHz
LO-to-RF Leakage = -81
dBm
SD Dynamic Range = 42 dB
@ 200 MHz
Power Dissipation = 106
mW
0.25-mm, 6-metal CMOS process
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Six-port Digital receiver
(Schiel et.al, E. Polytechnique de Montreal, CA)
50
LO
Input
50
100
Schottky
OPA-2658U High-speed
Diodes
OP-AmpCompensaters
HSMS-2850
G=20dB
TL3016
P1
RF
Input
P2
P3
Application
Specific
Six-port
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QPSK Decoder
Wideband
Matching Circuits
With TTL
Video
I&Q outputs
& Shottkey Diodes
Amplifiers
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Digital vs. Analog Conversion
15Msps ~ 60Msps
10bits ~ 14bits
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ADC directly behind the antenna of a 900
MHz GSM receiver would require N=18
for 100 dB SNR and a sample rate of 2
GHz, leading to a 36 Gbit/s ADC and a
power consumption is 10–100 W, which is
1000 times higher than existing low-IF
ADCs that consume around 10-15 mW.
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Wideband Spread
Spectrum Radio
x
o o
0
90
RF Filter LNA
f
C. Teuscher, N. Zhang,
D. Yee,
Prof. R.W. Brodersen
A/D
In Phase
(I)
A/D
Quadrature
(Q)
osc
AGC
x
Direct conversion architecture:
– Simplifies analog RF design
– Well-suited to single-chip CMOS integration
– No IF stage: eliminates image reject problem
– Primary challenge: DC offsets
Wideband CDMA zero IF receiver, Phillips
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Receiver Block Diagram
Ultimate objective: fully integrated,
single chip radio
RF
Filter
Channel
Estimation
RF to
Baseband
High
Speed
A/D
Analog IC
Carrier
and
Timing
Sync.
Digital IC
Adaptive
Multiuser
Detection
Data Out
3.3 Mbps
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Analog Baseband Section
b
Interference
Level
a
32 MHz
In band interference
Near band interference
Far band interference
1.96 GHz Frequency
1. Suppress out-of-band interference:
• RF filters do not provide adequate rejection
• Interference profile influences the design
2. High speed analog to digital conversion:
• Large dynamic range requirements
• Severe power constraints
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Required Filter
Rolloff (dB/decade)
Analog Baseband
300
50 MHz
converter
200
200 MHz
converter
100
0
-100
-60
-50
-40
-30
-20
-10
0
Out-of-Band Interference Level (dBm)
• Fundamental tradeoff between speed of ADC
and complexity of anti-alias filter
• Combined performance determines the maximum
out-of-band interference levels
• Current focus: energy-efficient implementations
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A/D Converter: Power vs.
Performance
A/D Converter
Performance
Summary
Commercially
Available
A/D
Converters (1998)
450
12 bit
Power (mW)
10 bit
300
8 bit
150
0
0
20
40
60
80
100
Speed (MHz)
Digital radios will require high speed, low power,
high resolution A/D converters
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Digital Baseband: Design
Issues
2X
Oversampled
Receive Signal
Carrier and
Timing
Synchronization
50 MHz
Adaptive
Channel
Estimation
Adaptive
Multiuser
25 MHz
Detection
Data Out
3.3 Mbps
• Algorithm: Pilot channel-assisted adaptive MUD
• Modes of operation: blind, decision-directed, training
sequence based
• Key design metrics: power, area, performance, cost
Use advanced semiconductor technology
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Architectural Design Choices
Prog Mem
Prog Mem
mP
Flexibility
Prog MemmP
ASIC
Direct
Mapped
Hardware
Satellite
Processor
Satellite Satellite
Processor Processor
MAC
Unit
Addr
Gen
Software
Programmable
DSP
Hardware
Reconfigurable
Processor
Power Consumption
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mP
General
Purpose
Microprocessor
Example: Adaptive Pilot
Correlator
Adaptive
Pilot
Correlator
2X Oversampled
Receive Signal
50 MHz
Carrier and
Timing
Synchronization
c1
25 MHz
Adaptive
Pilot
Correlator
. . . cL
Adaptive
Data
Correlator
Data Out
3.3 Mbps
• Each APC provides one multipath channel estimate
• Computational complexity of each APC:
– 300M multiplications per second
– 357M additions/subtractions per second
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Technology Comparison
TI Low-Power DSP* Direct Mapped IC
Process Technology
Linewidth
Threshold Voltage
Supply Voltage
Clock Rate
Wordlength
Flexibility
0.35mm
0.25mm
Dual V : 0.4V, 0.2V
0.5V
T
1V
1V
65 MHz
25 MHz
16
12
Software Prog.
Hard Wired
*TMS320LC54X
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Comparison: Power and
Die Area
Digital Baseband Receiver
Power
Area
DSP
Direct Mapped
1500 mW
3600 mm2
15 mW
8 mm2
DSP implementation is very inefficient:
• 100-150 times more power
• 450-700 times more area
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1st Approach: DSP
Implementation
• 35 parallel processors required for real-time
operation
• Each processor requires 1.6M transistors on a
31mm2 die
• Total power consumption: 460 mW
• Breakdown of execution time and power
consumption:
Execution Time Power Consumption
Arithmetic Instructions
35%
36%
Load/Store Instructions
29%
35%
Control Instructions
22%
17%
Memory Instructions
14%
12%
Total
100%
100%
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2nd Approach: Direct
Mapped Architecture
• Custom datapath design
• Optimized parallel hardware
with minimum control
• Reduced memory accesses
• Power and area dominated by
MACs, multipliers, and register
files
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Programmable vs. Dedicated
Power consumption:
– Memory access overhead
– Control overhead
– Wordlength overhead
– Assembly code optimization
Area:
– MAC units operate only 10% of the time
– On-chip memory consumes 75% of the area
– Arithmetic units less optimized
Flexibility:
– Level of programmability required (software,
hardware, other), Time to market issues
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Approach to Low Power
Design
Power = CL • VDD2 • fCLK
Minimize supply voltage:
– Architecture driven voltage scaling
Minimize physical capacitance:
– Minimum feature sizes
– Interconnect
Minimize switching activity:
– Algorithmic, architectural, numeric,
and circuit-level optimizations
– Power down
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Optimize design across all levels
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Supply Voltage Optimization
16 bit Ripple Adder
60
Delay (ns)
40
0.6 mm
process
0.25 mm
process
20
0
0.5
1
1.5
2
2.5
3
3.5
Supply Voltage (V)
• Use the lowest possible supply voltage that
satisfies throughput constraints: 1V
• Advanced process simultaneously improves
performance and reduces power consumption
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Finite Wordlength
Optimization
40
16 bit
12 bit
20
10 bit
Output SIR (dB)
30
10
8 bit
0
0
-10
40
1000
2000
Symbol Times
3000
• Fixed point arithmetic reduces power and
area requirements
• 12 bit wordlength suffices for this
application
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Power Amplifier
• PSK or QAM requires linear transmitter
amplifiers
• OFDM needs distortion reduction to
increase power conversion efficiency
• Adaptive signal processing is effective
• Monolithic SiGe HBT Power Amplifier
for Dual-Mode (CDMA/AMPS) Cellular
Handset
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IBM2018 – 800 MHz
CDMA/AMP Power Amplifier
• IS-95 CDMA/AMPS
824-849 MHz
• 2-stage LGA Module/
50 Ohm I/O
• Digital Power Up/Down
Control
• Analog Variable
Efficiency Control
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Conclusion
• Zero IF Architecture
• Required significant improvements in ADC
performance
power:10W – 5Gsample/w 18-bit
• The transmit part : Power Amplifier
• The receive part : Filter
Using Fast DSP
Digital
Analog
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