Transcript Lec3
EE 319K
Introduction to Embedded Systems
Lecture 3: Debugging, Arithmetic
Operations, More I/O, Switch and
LED interfacing
Bard, Gerstlauer, Valvano, Yerraballi
3-1
Agenda
Recap
GPIO
Logic and Shift Operations
Addressing Modes
Subroutines and the Stack
Introduction to C
Outline
Debugging
Arithmetic Operations
o Random Number Generator example
Digital Logic
o GPIO TM4C123/LM4F120 Specifics
Switch and LED interfacing
Bard, Gerstlauer, Valvano, Yerraballi
3-2
Debugging
Aka: Testing, Diagnostics,
Verification
Debugging Actions
Functional debugging,
input/output values
Performance debugging,
input/output values with
time
Tracing, measure
sequence of operations
Profiling,
o measure percentage for
tasks,
o time relationship
between tasks
Bard, Gerstlauer, Valvano, Yerraballi
Performance
measurement, how
fast it executes
Optimization, make
tradeoffs for overall
good
o
o
o
o
o
o
improve speed,
improve accuracy,
reduce memory,
reduce power,
reduce size,
reduce cost
3-3
Debugging Intrusiveness
Intrusive Debugging
degree of perturbation
caused by the debugging
itself
how much the debugging
slows down execution
Non-intrusive Debugging
characteristic or quality
of a debugger
allows system to operate
as if debugger did not
exist
e.g., logic analyzer, ICE,
BDM
Bard, Gerstlauer, Valvano, Yerraballi
Minimally intrusive
negligible effect on the
system being
debugged
e.g.,
dumps(ScanPoint) and
monitors
Highly intrusive
print statements,
breakpoints and
single-stepping
3-4
Debugging Aids in Keil
Interface
Breakpoints
Registers including xPSR
Memory and Watch Windows
Logic Analyzer, GPIO Panel
Single Step, StepOver, StepOut, Run, Run to
Cursor
Watching Variables in Assembly
EXPORT VarName[DATA,SIZE=4]
Command Interface (Advanced but useful)
WS 1, `VarName,0x10
LA (PORTD & 0x02)>>1
Bard, Gerstlauer, Valvano, Yerraballi
3-5
… Debugging
Instrumentation: Code we
add to the system that
aids in debugging
E.g., print statements
Good practice: Define
instruments with specific
pattern in their names
Use instruments that test
a run time global flag
o leaves a permanent
copy of the
debugging code
o causing it to suffer a
runtime overhead
o simplifies “on-site”
customer support.
Bard, Gerstlauer, Valvano, Yerraballi
Use conditional
compilation (or
conditional assembly)
o Keil supports
conditional assembly
o Easy to remove all
instruments
Visualization: How the
debugging information is
displayed
3-6
ARM ISA : ADD, SUB and CMP
ARITHMETIC INSTRUCTIONS
ADD{S} {Rd,} Rn,
ADD{S} {Rd,} Rn,
SUB{S} {Rd,} Rn,
SUB{S} {Rd,} Rn,
RSB{S} {Rd,} Rn,
RSB{S} {Rd,} Rn,
CMP Rn, <op2>
CMN Rn, <op2>
<op2>
#im12
<op2>
#im12
<op2>
#im12
Addition
C bit set if unsigned overflow
V bit set if signed overflow
Bard, Gerstlauer, Valvano, Yerraballi
;Rd
;Rd
;Rd
;Rd
;Rd
;Rd
;Rn
;Rn
=
=
=
=
=
=
-
Rn + op2
Rn + im12
Rn - op2
Rn - im12
op2 - Rn
im12 - Rn
op2
(-op2)
Subtraction
C bit clear if unsigned overflow
V bit set if signed overflow
3-7
ARM ISA : Multiply and Divide
32-BIT MULTIPLY/DIVIDE INSTRUCTIONS
MUL{S} {Rd,} Rn, Rm
MLA
Rd, Rn, Rm, Ra
MLS
Rd, Rn, Rm, Ra
UDIV
{Rd,} Rn, Rm
SDIV
{Rd,} Rn, Rm
;Rd
;Rd
;Rd
;Rd
;Rd
=
=
=
=
=
Rn * Rm
Ra + Rn*Rm
Ra - Rn*Rm
Rn/Rm unsigned
Rn/Rm signed
Multiplication does not set C,V bits
Bard, Gerstlauer, Valvano, Yerraballi
3-8
Random Number Generator
;Program demonstrates Arithmetic operations
; ADD, SUB, MUL and IDIV
; LR loss when sub calls sub - Solution
Seed
EQU
123456789
THUMB
AREA
DATA, ALIGN=2
EXPORT M [DATA,SIZE=4]
M
SPACE
4
ALIGN
AREA |.text|, CODE, READONLY, ALIGN=2
EXPORT Start
EXPORT M [DATA,SIZE=4]
; Need this to be able to watch RAM
; Variable M (in Assembly only)
Start LDR R2,=M
; R2 points to M
LDR R0,=Seed
; Initial seed
STR R0,[R2]
; M=Seed
loop
BL Random
; R0 has rand number
B
loop
Function Random
How it is called
How it returns
Bard, Gerstlauer, Valvano, Yerraballi
;------------Random-----------; Return R0= 32-bit random number
; Linear congruential generator
; from Numerical Recipes by Press et al.
Random LDR R2,=M
; R2 points to M
LDR R0,[R2] ; R0=M
LDR R1,=1664525
MUL R0,R0,R1 ; R0 = 1664525*M
LDR R1,=1013904223
ADD R0,R1 ; 1664525*M+1013904223
STR R0,[R2] ; store M
BX LR
Global variable M
How it is defined
How it is written
How it is read
3-9
Bus Driver
74HC125
Tristate Gate
A
G
Y
A
G
74HC244
8
8
Y
+3.3V
+3.3V
G
T5
T3
A
+3.3V
A
T6
T4
Y
T1
T7
G
T2
Bard, Gerstlauer, Valvano, Yerraballi
G
T8
3-10
Open Collector
A
Vcc
B 74LS05
20k
Vcc
74HC05
B
8k
B
A
Q
A
n-type
Q
2
1
Q2
4.5k
A
Low
High
Q2
B
off
HiZ
active Low
Used to control current to LED
Low allows current to flow to ground
HiZ prevents current from flowing
Bard, Gerstlauer, Valvano, Yerraballi
3-11
Input/Output: TM4C123
Systick
NVIC
Cortex M4
System Bus Interface
GPIO Port A
PA7
PA6
PA5/SSI0Tx
PA4/SSI0Rx
PA3/SSI0Fss
PA2/SSI0Clk
PA1/U0Tx
PA0/U0Rx
PC7
PC6
PC5
PC4
PC3/TDO/SWO
PC2/TDI
PC1/TMS/SWDIO
PC0/TCK/SWCLK
GPIO Port B
Eight
UARTs
Four
I2Cs
Four
SSIs
CAN 2.0
GPIO Port C
GPIO Port D
USB 2.0
Twelve
Timers
JTAG
Six
64-bit wide
GPIO Port E
PE5
PE4
PE3
PE2
PE1
PE0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
GPIO Port F
Two Analog
Comparators
ADC
2 channels
12 inputs
12 bits
Advanced High Performance Bus
PB7
PB6
PB5
PB4
PB3/I2C0SDA
PB2/I2C0SCL
PB1
PB0
Two PWM
Modules
PF4
PF3
PF2
PF1
PF0
6 General-Purpose
I/O (GPIO) ports:
• Four 8-bit ports
(A, B, C, D)
• One 6-bit port (E)
• One 5-bit port (F)
Advanced Peripheral Bus
Bard, Gerstlauer, Valvano, Yerraballi
3-12
TM4C123 I/O Pins
I/O Pin Characteristics
Set AFSEL to 0
Can be employed as an n-bit parallel interface
Pins also provide alternative functions:
o
o
o
o
o
o
o
o
o
o
o
UART
SSI
I2C
Timer
compare
PWM
ADC
signals
Analog
Comparator
QEI
USB
Ethernet
CAN
Universal asynchronous receiver/transmitter
Synchronous serial interface
Inter-integrated circuit
Periodic interrupts, input capture, and output
Pulse width modulation
Analog to digital converter, measure analog
Compare two analog signals
Quadrature encoder interface
Universal serial bus
High speed network
Controller area network
Set AFSEL
Bard, Gerstlauer, Valvano, Yerraballi
to 1
3-13
TM4C123 LaunchPad I/O Pins
IO
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD6
PD7
PE0
PE1
PE2
PE3
PE4
PE5
PF0
PF1
PF2
PF3
PF4
Ain
Ain10
Ain11
C1C1+
C0+
C0Ain7
Ain6
Ain5
Ain4
Ain3
Ain2
Ain1
Ain0
Ain9
Ain8
0
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
1
2
SSI0Clk
SSI0Fss
SSI0Rx
SSI0Tx
3
4
I2C1SCL
I2C1SDA
5
6
I2C0SCL
I2C0SDA
U4Rx
U4Tx
U3Rx
U3Tx
SSI3Clk
SSI3Fss
SSI3Rx
SSI3Tx
U2Rx
U2Tx
U7Rx
U7Tx
M0PWM2
M0PWM3
M0PWM0
M0PWM1
M0PWM6
M0PWM7
IDX1
PhA1
PhB1
SSI1Clk I2C3SCL M0PWM6 M1PWM0
SSI1Fss I2C3SDA M0PWM7 M1PWM1
SSI1Rx
M0Fault0
SSI1Tx
IDX0
M0Fault0
PhA0
PhB0
U5Rx
U5Tx
U1RTS SSI1Rx
U1CTS SSI1Tx
SSI1Clk
SSI1Fss
8
9
14
M1PWM2
M1PWM3
U1Rx
U1Tx
SSI2Clk
SSI2Fss
SSI2Rx
SSI2Tx
U1Rx
U1Tx
7
I2C2SCL M0PWM4 M1PWM2
I2C2SDA M0PWM5 M1PWM3
CAN0Rx
M1PWM4 PhA0
M1PWM5 PhB0
M0Fault0 M1PWM6
CAN0Tx
M1PWM7
M1Fault0 IDX0
T2CCP0
T2CCP1
T3CCP0
T3CCP1
T1CCP0
T1CCP1
T0CCP0
T0CCP1
WT0CCP0
WT0CCP1
WT1CCP0
WT1CCP1
WT2CCP0
WT2CCP1
WT3CCP0
WT3CCP1
WT5CCP0
WT5CCP1
T0CCP0
T0CCP1
T1CCP0
T1CCP1
T2CCP0
CAN0Rx
CAN0Tx
U1RTS
U1CTS
USB0epen
USB0pflt
USB0epen
USB0pflt
NMI
CAN0Rx
CAN0Tx
NMI
USB0epen
C0o
C1o
TRD1
TRD0
TRCLK
3-14
TM4C123 I/O registers
Address
$400F.E608
$400F.EA08
$4005.8000
$4005.9000
$4005.A000
$4005.B000
$4005.C000
$4005.D000
base+$3FC
base+$400
base+$420
base+$510
base+$51C
base+$524
base+$528
base+$52C
base+$520
7
6
5
GPIOF
GPIOF
4
GPIOE
GPIOE
3
GPIOD
GPIOD
2
GPIOC
GPIOC
1
GPIOB
GPIOB
0
GPIOA
GPIOA
DATA
DIR
SEL
PUE
DEN
CR
AMSEL
DATA
DIR
SEL
PUE
DEN
CR
AMSEL
DATA
DIR
SEL
PUE
DEN
CR
AMSEL
DATA
DIR
SEL
PUE
DEN
CR
AMSEL
DATA
DIR
SEL
PUE
DEN
CR
AMSEL
DATA
DIR
SEL
PUE
DEN
CR
AMSEL
DATA
DIR
SEL
PUE
DEN
CR
AMSEL
DATA
DIR
SEL
PUE
DEN
CR
AMSEL
31-28
PMC7
27-24
PMC6
23-20
PMC5
19-16
15-12
PMC4
PMC3
LOCK (32 bits)
11-8
PMC2
7-4
PMC1
3-0
PMC0
• Four 8-bit ports (A, B, C, D)
• One 6-bit port (E)
• One 5-bit port (F)
Bard, Gerstlauer, Valvano, Yerraballi
Name
SYSCTL_RCGCGPIO_R
SYSCTL_PRGPIO_R
PORTA base address
PORTB base address
PORTC base address
PORTD base address
PORTE base address
PORTF base address
GPIO_PORTx_DATA_R
GPIO_PORTx_DIR_R
GPIO_PORTx_AFSEL_R
GPIO_PORTx_PUR_R
GPIO_PORTx_DEN_R
GPIO_PORTx_CR_R
GPIO_PORTx_AMSEL_R
GPIO_PORTx_PCTL_R
GPIO_PORTx_LOCK_R
• PA1-0 to COM port
• PC3-0 to debugger
• PD5-4 to USB device
3-15
Switch Configuration
negative – pressed = ‘0’
Bard, Gerstlauer, Valvano, Yerraballi
positive – pressed = ‘1’
3-16
Switch Configuration
+3.3V
10k
s
+3.3V
TM4C
t
Input port
+3.3V
TM4C
10k
s
Input port
0.0V
Pressed
+3.3V
TM4C
10k
s
Input port
3.3V
Not pressed
Bard, Gerstlauer, Valvano, Yerraballi
Input port
10k
Positive logic
Negative logic
Negative Logic s
– pressed, 0V, false
– not pressed, 3.3V, true
TM4C
Positive Logic t
– pressed, 3.3V, true
– not pressed, 0V, false
+3.3V
t
TM4C
3.3V
Input port
10k
Pressed
+3.3V
t
TM4C
0V
Input port
10k
Not pressed
3-17
LED Interfacing
LED current v. voltage
Brightness = power = V*I
anode (+)
cathode (1)
“big voltage connects to big pin”
Bard, Gerstlauer, Valvano, Yerraballi
3-18
LED Configuration
Current
I
2
(mA) 1
+ a
-
I
k
voltage
0
Out
LM3S
or
TM4C
high
R
1mA
LED
Out
1.5 1.6 1.7
V (volts)
(a) LED curve
(b) Positive logic interface
Bard, Gerstlauer, Valvano, Yerraballi
+3.3V
R
LM3S
or
TM4C
1mA
LED
low
(c) Negative logic interface
3-19
LED Interfacing
R = (3V – 1.5)/0.001
= 1.5 kOhm
Out
LM3S
or
TM4C
high
R
1mA
R = (5.0-2-0.5)/0.01
= 250 Ohm
LM3S
or
TM4C
LED
LED current < 8 ma
Out
+5V
R
7406
+5V
high
0.5V
10mA
LED
LED current > 8 ma
LED may contain several diodes in series
Bard, Gerstlauer, Valvano, Yerraballi
3-20
LaunchPad Switches and LEDs
R1 0
Serial
R29
+5
0
USB
R25
0
R9
0
R10 0
TM4C123 PF0
PF4
R13 0
PA1
PA0
Green
PB1
PD5
R12
PD4
PF3
PB0
0
PD0
R11
PF2
PB6
0
PD1
R2
PF1
PB7
0
5V
Blue
330
330
Red
330
SW1
SW2
DTC114EET1G
The switches on the LaunchPad
Negative logic
Require internal pull-up (set bits in PUR)
The PF3-1 LEDs are positive logic
Bard, Gerstlauer, Valvano, Yerraballi
3-21
Initialization Ritual
• Initialization (executed once at beginning)
1. Turn on Port F clock in SYSCTL_RCGCGPIO_R
Wait two bus cycles (two NOP)
2. Unlock PF0 (PD7 also needs unlocking)
3. Clear AMSEL to disable analog
4. Clear PCTL to select GPIO
5. Set DIR to 0 for input, 1 for output
6. Clear AFSEL bits to 0 to select regular I/O
7. Set PUE bits to 1 to enable internal pull-up
8. Set DEN bits to 1 to enable data pins
• Input from switches, output to LED
10. Read/write GPIO_PORTF_DATA_R
Prog 4.1, show PortF_Init function in InputOutput_xxxasm
Bard, Gerstlauer, Valvano, Yerraballi
3-22
I/O Port Bit-Specific
I/O Port bit-specific
addressing is used to
access port data
register
Define address offset as
4*2b, where b is the
selected bit position
256 possible bit
combinations (0-8)
Add offsets for each bit
selected to base
address for the port
Example: PF4 and PF0
Port F = 0x4005.D000
0x4005.D000+0x0004+0x0040
= 0x4005.D044
Provides friendly and atomic
access to port pins
Show PortF_Input2 function in InputOutput_xxxasm
Bard, Gerstlauer, Valvano, Yerraballi
3-23