Transcript Chapter 5 Synchronous Sequential Logic

Princess Sumaya Univ.
Computer Engineering Dept.
Chapter 5:
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Sequential Circuits
 Asynchronous
Inputs
Combinational
Circuit
Outputs
Memory
Elements
 Synchronous
Inputs
Outputs
Combinational
Circuit
Clock
Flip-flops
1 / 60
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Latches
 SR Latch
R
S
0
S R Q0
0 0 0
0
Q
0
Q’
1
Q = Q0
Q
Q
0
1
Initial Value
2 / 60
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Latches
 SR Latch
R
S
0
S R Q0
0 0 0
0 0 1
1
Q
0
1
Q’
1
0
Q = Q0
Q = Q0
Q
Q
0
0
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4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Latches
 SR Latch
R
S
1
0
S
0
0
0
R
0
0
1
Q0
0
1
0
Q
0
1
0
Q’
1
0
1
Q = Q0
Q=0
Q
Q
0
1
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4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Latches
 SR Latch
R
S
1
1
Q
S
0
0
0
0
R
0
0
1
1
Q0
0
1
0
1
Q
0
1
0
0
Q’
1
0
1
1
Q = Q0
Q=0
Q=0
Q
0
0
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4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Latches
 SR Latch
0
R
S
0
Q
S
0
0
0
0
1
R
0
0
1
1
0
Q0
0
1
0
1
0
Q
0
1
0
0
1
Q’
1
0
1
1
0
Q = Q0
Q=0
Q=1
Q
1
1
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4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Latches
 SR Latch
0
R
S
1
Q
S
0
0
0
0
1
1
R
0
0
1
1
0
0
Q0
0
1
0
1
0
1
Q
0
1
0
0
1
1
Q’
1
0
1
1
0
0
Q = Q0
Q=0
Q=1
Q=1
Q
1
0
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4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Latches
 SR Latch
1
R
S
0
Q
S
0
0
0
0
1
1
1
R
0
0
1
1
0
0
1
Q0
0
1
0
1
0
1
0
Q
0
1
0
0
1
1
0
Q’
1
0
1
1
0
0
0
Q = Q0
Q=0
Q=1
Q = Q’
Q
1
10
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4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Latches
 SR Latch
1
R
S
10
Q
Q
1
S
0
0
0
0
1
1
1
1
R
0
0
1
1
0
0
1
1
Q0
0
1
0
1
0
1
0
1
Q
0
1
0
0
1
1
0
0
Q’
1
0
1
1
0
0
0
0
Q = Q0
Q=0
Q=1
Q = Q’
Q = Q’
0
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4241 – Digital Logic Design
Computer Engineering Dept.
Latches
 SR Latch
S R
R
Q
S
Q
S
Q
R
Q
Q
Q0
No change
Reset
0
Set
1
Invalid
Q=Q’=0
0
0
1
1
0
1
0
1
S
0
0
1
1
Q
R
Invalid
0 Q=Q’=1
Set
1
1
Reset
0
0
Q0
No change
1
10 / 60
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Latches
 SR Latch
S R
R
Q
S
Q
S
R
Q
Q
0
0
1
1
0
1
0
1
S’ R’
0
0
1
1
0
1
0
1
Q
Q0
No change
Reset
0
Set
1
Invalid
Q=Q’=0
Q
Invalid
Q=Q’=1
Set
1
Reset
0
Q0
No change
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Controlled Latches
 SR Latch with Control Input
R
R
S
Q
C
S
Q
C
S
R
Q
S
C S R
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
R
Q
Q0
Q0
0
1
Q=Q’
Q
No change
No change
Reset
Set
Invalid
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Controlled Latches
 D Latch (D = Data)
Timing Diagram
C
S
D
Q
D
C
R
Q
Q
t
C D
0 x
1 0
1 1
Q
Q0
0
1
No change
Reset
Set
Output may
change
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4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Controlled Latches
 D Latch (D = Data)
Timing Diagram
C
S
D
Q
D
C
R
C D
0 x
1 0
1 1
Q
Q
Q0
0
1
No change
Reset
Set
Q
Output may
change
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Flip-Flops
 Controlled latches are level-triggered
C
Flip-Flops are edge-triggered
CLK
Positive Edge
CLK
Negative Edge
15 / 60
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Flip-Flops
 Master-Slave D Flip-Flop
D
D
C
D Latch
(Master)
Q
D
C
D Latch
(Slave)
Master
CLK
Q
Q
Slave
CLK
D
Looks like it is negative
edge-triggered
QMaster
QSlave
16 / 60
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4241 – Digital Logic Design
Computer Engineering Dept.
Flip-Flops
 Edge-Triggered D Flip-Flop
D
Q
Q
Q
Positive Edge
CLK
Q
D
Q
Q
D
Negative Edge
17 / 60
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Computer Engineering Dept.
Flip-Flops
 JK Flip-Flop
J
D
Q
Q
Q
Q
K
CLK
J
Q
K
Q
D = JQ’ + K’Q
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Computer Engineering Dept.
Flip-Flops
 T Flip-Flop
T
J
K
Q
D
T
Q
Q
D = JQ’ + K’Q
D = TQ’ + T’Q = T  Q
Q
T
Q
Q
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Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Flip-Flop Characteristic Tables
D
Q
Q
J
Q
K
Q
T
Q
Q
D
0
1
J
0
0
1
1
T
0
1
Q(t+1)
0
1
Reset
Set
K Q(t+1)
0
Q(t)
1
0
0
1
1 Q’(t)
No change
Reset
Set
Toggle
Q(t+1)
Q(t)
Q’(t)
No change
Toggle
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Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Flip-Flop Characteristic Equations
D
Q
Q
J
Q
K
Q
T
Q
Q
D
0
1
J
0
0
1
1
Q(t+1)
0
1
K Q(t+1)
0
Q(t)
1
0
0
1
1 Q’(t)
T
0
1
Q(t+1)
Q(t)
Q’(t)
Q(t+1) = D
Q(t+1) = JQ’ + K’Q
Q(t+1) = T  Q
21 / 60
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Flip-Flop Characteristic Equations
 Analysis / Derivation
J
K
Q
Q
J
0
0
0
0
1
1
1
1
K Q(t) Q(t+1)
0 0
0
0 1
1
1 0
1 1
0 0
0 1
1 0
1 1
No change
Reset
Set
Toggle
22 / 60
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4241 – Digital Logic Design
Computer Engineering Dept.
Flip-Flop Characteristic Equations
 Analysis / Derivation
J
K
Q
Q
J
0
0
0
0
1
1
1
1
K Q(t) Q(t+1)
0 0
0
0 1
1
1 0
0
1 1
0
0 0
0 1
1 0
1 1
No change
Reset
Set
Toggle
23 / 60
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Flip-Flop Characteristic Equations
 Analysis / Derivation
J
K
Q
Q
J
0
0
0
0
1
1
1
1
K Q(t) Q(t+1)
0 0
0
0 1
1
1 0
0
1 1
0
0 0
1
0 1
1
1 0
1 1
No change
Reset
Set
Toggle
24 / 60
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4241 – Digital Logic Design
Computer Engineering Dept.
Flip-Flop Characteristic Equations
 Analysis / Derivation
J
K
Q
Q
J
0
0
0
0
1
1
1
1
K Q(t) Q(t+1)
0 0
0
0 1
1
1 0
0
1 1
0
0 0
1
0 1
1
1 0
1
1 1
0
No change
Reset
Set
Toggle
25 / 60
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4241 – Digital Logic Design
Computer Engineering Dept.
Flip-Flop Characteristic Equations
 Analysis / Derivation
J
K
Q
Q
J
0
0
0
0
1
1
1
1
K Q(t) Q(t+1)
0 0
0
0 1
1
1 0
0
1 1
0
0 0
1
0 1
1
1 0
1
1 1
0
K
0
J 1
1
1
0
0
0
1
Q
Q(t+1) = JQ’ + K’Q
26 / 60
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Flip-Flops with Direct Inputs
 Asynchronous Reset
D
Q
R’
0
D CLK Q(t+1)
x
x
0
Q
R
Reset
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Computer Engineering Dept.
Flip-Flops with Direct Inputs
 Asynchronous Reset
D
Q
Q
R
R’
0
1
1
D CLK Q(t+1)
x
x
0
↑
0
0
↑
1
1
Reset
28 / 60
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Flip-Flops with Direct Inputs
 Asynchronous Preset and Clear
Preset
PR
D Q
PR’ CLR’ D CLK Q(t+1)
1
0
x
x
0
Q
CLR
Reset
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Computer Engineering Dept.
Flip-Flops with Direct Inputs
 Asynchronous Preset and Clear
Preset
PR
D Q
PR’ CLR’ D CLK Q(t+1)
1
0
x
x
0
x
0
1
x
1
Q
CLR
Reset
30 / 60
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Computer Engineering Dept.
Flip-Flops with Direct Inputs
 Asynchronous Preset and Clear
Preset
PR
D Q
Q
CLR
PR’ CLR’ D CLK Q(t+1)
1
0
x
x
0
x
0
1
x
1
↑
1
1
0
0
↑
1
1
1
1
Reset
31 / 60
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Computer Engineering Dept.
Analysis of Clocked Sequential Circuits
 The State
● State = Values of all Flip-Flops
x
Example
D
Q
A
Q
AB=00
D
CLK
Q
B
Q
y
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Computer Engineering Dept.
Analysis of Clocked Sequential Circuits
 State Equations
x
A(t+1) = DA
D
= A(t) x(t)+B(t) x(t)
Q
A
Q
=Ax+Bx
D
B(t+1) = DB
= A’(t) x(t)
= A’ x
CLK
Q
B
Q
y
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’
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Computer Engineering Dept.
Analysis of Clocked Sequential Circuits
 State Table (Transition Table)
Present
Input
State
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
t
x
0
1
0
1
0
1
0
1
Next
State
A
0
0
0
1
0
1
0
1
t+1
B
0
1
0
1
0
0
0
0
x
D
Output
y
0
0
1
0
1
0
1
0
t
Q
A
Q
D
CLK
Q
B
Q
y
A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
34 / 60
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Computer Engineering Dept.
Analysis of Clocked Sequential Circuits
 State Table (Transition Table)
x
Present
State
A
0
0
1
1
t
B
0
1
0
1
Next State
Output
x=0 x=1 x=0 x=1
A
0
0
0
0
B
0
0
0
0
A
0
1
1
1
t+1
B
1
1
0
0
y
0
1
1
1
y
0
0
0
0
t
D
Q
A
Q
D
CLK
Q
B
Q
y
A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
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Analysis of Clocked Sequential Circuits
 State Diagram
Present
State
input/output
AB
0/0
1/0
0/1
00
Next State
x=0
Output
x=1
x=0
x=1
A B
A B A B
y
y
0 0
0
0
0
1
0
0
0 1
0
0
1
1
1
0
1 0
0
0
1
0
1
0
1 1
0
0
1
0
1
0
10
x
D
0/1
1/0
0/1
CLK
11
A
Q
1/0
D
01
Q
Q
B
Q
y
1/0
36 / 60
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4241 – Digital Logic Design
Computer Engineering Dept.
Analysis of Clocked Sequential Circuits
 D Flip-Flops
Example:
Present
Input
State
A
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
y
0
1
0
1
0
1
0
1
Next
State
A
0
1
1
0
1
0
0
1
x
y
D
CLK
Q
A
Q
A(t+1) = DA = A  x  y
01,10
00,11
0
1
00,11
01,10
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Analysis of Clocked Sequential Circuits
 JK Flip-Flops
Example:
x
Present
Next
I/P
State
State
A B x A B
0 0 0 0 1
Flip-Flop
Inputs
JA KA JB KB
0 0 1 0
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
J
Q
K
Q
J
Q
K
Q
A
B
CLK
JA = B
JB = x’
KA = B x’
KB = A  x
A(t+1) = JA Q’A + K’A QA
= A’B + AB’ + Ax
B(t+1) = JB Q’B + K’B QB
= B’x’ + ABx + A’Bx’
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Analysis of Clocked Sequential Circuits
 JK Flip-Flops
x
Example:
Present
Next
I/P
State
State
A B x A B
0 0 0 0 1
Flip-Flop
Inputs
JA KA JB KB
0 0 1 0
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
J
Q
K
Q
J
Q
K
Q
A
B
CLK
1
0
1
11
00
0
0
01
0
10
1
1
39 / 60
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Analysis of Clocked Sequential Circuits
 T Flip-Flops
x
T
Present
Next
F.F
I/P
O/P
State
State Inputs
A B x A B TA TB y
0
0 0 0 0 0 0 0
0
0 0 1 0 1 0 1
1
A
y
R Q
Example:
0
Q
0
0
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
0
0
0
1
0
1
1
1
0
1
0
1
1
0
1
1
0
0
1
1
1
1
0
0
1
1
1
T
Q
B
R Q
CLK
TA = B x
y =AB
Reset
TB = x
A(t+1) = TA Q’A + T’A QA
= AB’ + Ax’ + A’Bx
B(t+1) = TB Q’B + T’B QB
=xB
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Analysis of Clocked Sequential Circuits
 T Flip-Flops
x
T
Present
Next
F.F
I/P
O/P
State
State Inputs
A B x A B TA TB y
0
0 0 0 0 0 0 0
0
0 0 1 0 1 0 1
0
1
0
0
1
0
0
0
0
1
1
1
0
1
1
0
1
0
0
1
0
0
0
0
1
0
1
1
1
0
1
0
1
1
0
1
1
0
0
1
0
1
1
1
1
1
A
y
R Q
Example:
1
Q
0
T
Q
B
R Q
CLK
Reset
0/0
0/0
00
1/0
01
1/1
1/0
11
0/1
10
1/0
0/0
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Mealy and Moore Models
Mealy
Present
State
A B
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
I/P
x
0
1
0
1
0
1
0
1
Next
O/P
State
A B y
0 0 0
0 1 0
0 0 1
1 1 0
0 0 1
1 0 0
0 0 1
1 0 0
For the same state,
the output changes with the input
Moore
Present
State
A B
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
I/P
x
0
1
0
1
0
1
0
1
Next
O/P
State
A B y
0 0 0
0 1 0
0 1 0
1 0 0
1 0 0
1 1 0
1 1 1
0 0 1
For the same state,
the output does not change with the input
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Moore State Diagram
State / Output
0
0
1
00/0
01/0
1
1
11/1
10/0
1
0
0
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Timing Diagram
1
0
00/0
A
x
0
01/0
y
0
B
1
0
11/1
No effect
10/0
1
1
CLK
x
State
A
0
0
1
0
0
0
B
0
1
0
0
1
1
y
44 / 60
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Timing Diagram
1/0
0/0
00
A
x
0/0
01
y
B
0/0
11
1/1
1/0
0/0
10
1/1
CLK
x
State
A
1
B
0
y
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Design of Clocked Sequential Circuits
 Example:
Detect 3 or more consecutive 1’s
1
0
S0 / 0
S1 / 0
0
0
1
0
S3 / 1
1
S2 / 0
State A B
S0
0 0
S1
0 1
S2
1 0
S3
1 1
1
46 / 60
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Design of Clocked Sequential Circuits
 Example:
Detect 3 or more consecutive 1’s
Present
Input
State
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
Next
State
A
0
0
0
1
0
1
0
1
B
0
1
0
0
0
1
0
1
Output
y
0
0
0
0
0
0
1
1
1
0
S0 / 0
S1 / 0
0
0
0
S3 / 1
1
1
S2 / 0
1
47 / 60
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Design of Clocked Sequential Circuits
 Example:
Detect 3 or more consecutive 1’s
Present
Input
State
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
Next
State
A
0
0
0
1
0
1
0
1
B
0
1
0
0
0
1
0
1
Output
y
0
0
0
0
0
0
1
1
Synthesis using D Flip-Flops
A(t+1) = DA (A, B, x)
= ∑ (3, 5, 7)
B(t+1) = DB (A, B, x)
= ∑ (1, 5, 7)
y (A, B, x) = ∑ (6, 7)
48 / 60
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Design of Clocked Sequential Circuits with D F.F.
 Example:
Detect 3 or more consecutive 1’s
Synthesis using D Flip-Flops
DA (A, B, x) = ∑ (3, 5, 7)
= Ax + B x
DB (A, B, x) = ∑ (1, 5, 7)
B
0 0 1 0
A 0 1 1 0
x
0 1 0 0
= A x + B’ x
y (A, B, x) = ∑ (6, 7)
=AB
B
B
A 0 1 1 0
x
0 0 0 0
A 0 0 1 1
x
49 / 60
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Design of Clocked Sequential Circuits with D F.F.
 Example:
Detect 3 or more consecutive 1’s
Synthesis using D Flip-Flops
DA = A x + B x
DB = A x + B’ x
D
x
Q
A
Q
y =AB
y
D
CLK
Q
B
Q
50 / 60
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Flip-Flop Excitation Tables
Present Next
State State
Q(t) Q(t+1)
0
0
0
1
1
0
1
1
F.F.
Input
D
0
1
0
1
Present Next
State State
F.F.
Input
Q(t) Q(t+1) J K
0 x
0
0
1 x
0
1
1
0
x 1
1
1
x 0
Q(t) Q(t+1)
0
0
0
1
1
0
1
1
0 0 (No change)
0 1 (Reset)
1 0 (Set)
1 1 (Toggle)
0 1 (Reset)
1 1 (Toggle)
0 0 (No change)
1 0 (Set)
T
0
1
1
0
51 / 60
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Design of Clocked Sequential Circuits with JK F.F.
 Example:
Detect 3 or more consecutive 1’s
Present
Input
State
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
Next
State
A
0
0
0
1
0
1
0
1
B JA
0 0
1 0
0 0
0 1
0 x
1 x
0 x
1 x
Flip-Flop
Inputs
KA
x
x
x
x
1
0
1
0
JB KB
0 x
1 x
x 1
x 1
0 x
1 x
x 1
x 0
Synthesis using JK F.F.
JA (A, B, x) = ∑ (3)
dJA (A, B, x) = ∑ (4,5,6,7)
KA (A, B, x) = ∑ (4, 6)
dKA (A, B, x) = ∑ (0,1,2,3)
JB (A, B, x) = ∑ (1, 5)
dJB (A, B, x) = ∑ (2,3,6,7)
KB (A, B, x) = ∑ (2, 3, 6)
dKB (A, B, x) = ∑ (0,1,4,5)
52 / 60
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Design of Clocked Sequential Circuits with JK F.F.
 Example:
Detect 3 or more consecutive 1’s
Synthesis using JK Flip-Flops
JA = B x
KA = x’
JB = x
KB = A’ + x’
x
CLK
B
0 0 1 0
x x x x
A 1 0 0 1
x
B
x x 1 1
A x x 0 1
x
J
Q
A
K
Q
y
A x x x x
x
B
0 1 x x
B
A 0 1 x x
x
J
Q
K
Q
B
53 / 60
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Design of Clocked Sequential Circuits with T F.F.
 Example:
Detect 3 or more consecutive 1’s
Present
Input
State
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
Next
State
A
0
0
0
1
0
1
0
1
B
0
1
0
0
0
1
0
1
F.F.
Input
TA
0
0
0
1
1
0
1
0
TB
0
1
1
1
0
1
1
0
Synthesis using T Flip-Flops
TA (A, B, x) = ∑ (3, 4, 6)
TB (A, B, x) = ∑ (1, 2, 3, 5, 6)
54 / 60
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Design of Clocked Sequential Circuits with T F.F.
 Example:
Detect 3 or more consecutive 1’s
Synthesis using T Flip-Flops
TA = A x’ + A’ B x
TB = A’ B + B  x
B
T
x
B
0 0 1 0
0 1 1 1
A 1 0 0 1
x
A 0 1 0 1
x
T
Q
A
Q
y
Q
B
Q
CLK
55 / 60
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Homework
 Mano
● Chapter 5
♦ 5-1
♦ 5-3
♦ 5-6
♦ 5-8
♦ 5-9
56 / 60
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Homework
5-1
The D latch is constructed with four NAND gates and an
inverter. Consider the following three other ways for
obtaining a D latch. In each case, draw the logic diagram
and verify the circuit operation.
(a) Use NOR gates for the SR latch part and AND gates
for the other two. An inverter may be needed.
(b) Use NOR gates for all four gates. Inverters may be
needed.
(c) Use four NAND gates only (without an inverter). This
can be done by connecting the output of the upper gate
that goes to the SR latch to the input of the lower gate
instead of the inverter output.
57 / 60
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Homework
5-3
Show that the characteristic equation for the complement
output of a JK flip-flop is
Q’(t+1) = J’Q + K Q
5-6
A sequential circuit with two D flip-flops, A and B; two
inputs, x and y; and one output, z, is specified by the
following next-state and output equations:
A(t+1) = x’ y + x A
B(t+1) = x’ B + x A
z=B
(a) Draw the logic diagram of the circuit.
(b) List the state table for the sequential circuit.
(c) Draw the corresponding state diagram.
58 / 60
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Homework
5-8
Derive the state table and the state diagram of the
sequential shown circuit. Explain the function that the
circuit performs.
B
A
Q
T
Q
Q
Q
T
CLK
59 / 60
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Homework
5-9
A sequential circuit has two JK flip-flops A and B and one
input x. The circuit is described by the following flip-flop
input equations:
JA = x
KA = B’
JB = x
KB = A
(a) Derive the state equations A(t+1) and B(t+1) by
substituting the input equations for the J and K
variables.
(b) Draw the state diagram of the circuit.
60 / 60