Transcript Slides
Vertically scaled 5 nm GaN channel Enhancement-mode N-polar GaN MOS-HFET with 560 mS/mm g m and 0.76
W
-mm R on
Uttam Singisetti*, Man Hoi Wong, Jim Speck, and Umesh Mishra ECE and Materials Departments University of California, Santa Barbara, CA 2011 Device Research Conference Santa Barbara, CA, USA
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Outline
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Next generation GaN electronic devices
•
N-polar GaN HEMTs
•
Vertically scaled channel devices
•
Results and Conclusion
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Next-generation mm-wave GaN devices John Albrecht, DARPA 1.3 W at 75 GHz Fujitsu, CSIC 2010 3 W at 87 GHz Caltech, HRL ISSSTT, 2011 W-band GaN power amplifiers − GaN HEMTs: Power-switching, microwave, W-band power amplifiers −Future GaN devices for beyond mm-wave and to sub-mm-wave bands −Higher operating voltages than traditional III-Vs and Si
mixed signal ICs robust and rugged
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Device goals and structure −Aggressive dimensional scaling (L
g and L sd )
−Vertical scaling with back-barrier and high-k dielectric − Parasitic resistances and capacitances scaling −Maintain high breakdown voltage 4
Ultra-scaled N-polar HEMTs No electron barrier N-polar inverted HEMT
N-polar GaN
− No barrier to electron on top of 2-DEG
low resistance contacts (0.027
W
-mm) 1 grading to narrowgap InN
− AlGaN back
confinement of 2-DEG, control short channel effects 2
− Record high g
m = 1105 mS/mm demonstrated 4 in D-mode
− E-mode devices 1. S.Dasgupta, APL 2010, 2. S. Rajan, IEEE TED 2011 3. NIdhi, DRC 2011 5
E-mode device structure and design
0 -2 -4 -6 4 2 AlN GaN AlN Al x Ga 1-x N:Si 0.05
E C E F Top AlN depletes 2-DEG under gate E V 4 3 2 E C 1 0 E F -1 -2 E V -3 -4 20 SiN x GaN AlN n(x) 40 60 Depth (nm) GaN:Si 80 GaN
Under sidewall
AlN removed under sidewall
3.0
2.5
2.0
1.5
1.0
0.5
0.0
100 0 5 10 15 20 25 30 35 40 -2 -3 -4 4 3
AlN
2 1
InN
0
n
+ Graded InGaN (In: 0% to 65%) GaN channel
-1 0 20 40 60 Depth (nm) 80
GaN:Si
100
E F
Under S/D contacts*
* S.Dasgupta, APL 2010 6
Short channel effect and vertical scaling 20 nm GaN channel 1 8 nm GaN channel 2
V t roll-off with gate length
• V th roll off with gate length
Poor saturation at sub-100nm L g
• Vertical scaling needed to maintain E-mode at sub-50 nm gate lengths • Vertical scaling for high R ds at sub-50-nm gate lengths
Need 5 nm GaN channel for sub-50 nm devices
1. U.Singisetti, EDL 2010, 2. U.Singisetti, APEX 2011 7
Ultra-thin channel challenges: Mobility
QW thickness flutuations
GaN
• Need 5 nm thick GaN channel for sub-50 nm devices • Mobility drops with decreasing GaN channel thickness • Interface roughness, surface roughness scattering increases* * U.Singisetti, ISCS 2011 8
Mobility dependence on Si doping
Si : 5 e18 cm -3 Si : 2 e 19 cm -3 • Low mobility in high-3D Si density samples • High Si density may lead to rougher interface 9
Ultra-thin channel challenges: surface depletion • Surface depletion increases in thin channels • Lower charge in the access regions lead to higher source resistance 10
5nm-GaN channel device design
• Graded back-barrier high mobility and t reduce the effect of trap* • 4.5 nm of Al 2 O 3 gate dielectric • 1.6×10 13 cm -2 in the sidewall access regions after top-AlN etch * M -H Wong, DRC 2011.
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Device fabrication process*
* U.Singisetti, EDL 2010.
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DC characteristics
• Reduced short channel effects due to vertical scaling and graded barrier 1 • Peak g m = 560 mS/mm, peak I d = 1.3 A/mm • Positive threshold voltage of 1.3 V * M -H Wong, DRC 2011.
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DC characteristics: R
on
and R
s
InN Gate InN No InN Gate
• Record low R on = 0.61 W -mm* for L g = 115 nm • InN growth optimization for complete coverage near the gate • Regrowth sheet resistance = 100 W /sq, r c = 5 W -mm 14
RF performance: peak f
t • peak f t = 115 GHz at V ds = 4.5 V and V gs = 2.5 V • low f max = 30 GHz due to thin W gate ( ~ 1500 W /sq) 15
RF performance : small-signal model
Measured (circles) Modeled (line)
S 21 /5 S 12 *3 S 11 S 22 • Equivalent circuit model 16
RF performance: bias dependence
• V gs corrosponding to peak f t is 2.5 V • Absence of drain delay 17
Conclusions and future work • Demonstrated vertically scaled 5-nm GaN channel MOS-HFET devices • E-mode with V th = 1.3 V, peak g m = 560 mS/mm, peak I d = 1.3 A/mm • Record low R on = 0.61 W -mm, for 115 nm E-mode GaN HEMTs • peak f t = 115 GHz for 120 nm gate length device Future work • Scale the gate length to 50 nm • Top gate for f max • Scale the gate dielectric (HfO 2 , ZrO 2 ) This work was supported by DARPA NEXT program 18
New measurements post DRC • peak f t = 122 GHz at V ds = 5.5 V and V gs = 2.5 V • f t -L g product of 14 GHz m m 19
New measurements post DRC • maximum I on /I off ratio ~ 2×10 5 • Breakdown voltage 8. 6 V • dielectric breakdown 20