Transcript Chapter 6: Virtex Memory

CHAPTER 6
Virtex Memory
Agenda
• RAM Applications
• LUT RAM
– SRL 16
– Other uses of LUT RAM (FIFO focus)
• Block RAM
• Inside Block RAM Cells
RAM Applications
•
•
•
•
•
•
•
•
•
Operand stacks
Register files
Instruction caches
DMA buffers
Instruction memories
State tables
Logic functions
Message buffers
Virtual channels
• Video line buffers
• Digital delay lines
• RAMDAC color
mapping tables
• Test vector buffers
• PCI configuration
space
• Sequential machines
• More . . .
LUT/RAM/Shifter Structure
SRAM DATA
CONFIGURATION CLOCK
SHIFT DATA
CONFIGURATION DATA
CLK
WE
A0
A1
A2
A3
CLK
WE
A0
A1
A2
A3
CLK
WE
A0
A1
A2
A3
CLK
D Q
CONFIGURATION
SHIFTER
SRAM
CELL 0
CD
D Q
CELL 1
CD
D Q
DATAOUT
CELL 2
TO CELL 3
FROM CELL 13
WE
A0
A1
A2
A3
CLK
WE
A0
A1
A2
A3
CLK
CD
D Q
CELL 14
CD
D Q
CELL 15
TO NEXT LUT SHIFT INPUT SELECT MUX
A0
A1
A2
A3
Linear Feedback Shift Regs.
Galois
style
Fibonacci
style
Multiple SRL16E LFSR
Virtex 5 SRL 32s Cascaded
Push/Pop Shifter
CLOCK
(Push and Pop)
INPUT
DATA
BYTE
DI0
D Q D Q D Q D Q D Q
D Q D Q D Q D Q D Q
D Q
D Q
D Q
D Q
D Q
D Q
DO0
DI1
D Q D Q D Q D Q D Q
D Q D Q D Q D Q D Q
D Q
D Q
D Q
D Q
D Q
D Q
DO1
DI2
D Q D Q D Q D Q D Q
D Q D Q D Q D Q D Q
D Q
D Q
D Q
D Q
D Q
D Q
DO2
DI3
D Q D Q D Q D Q D Q
D Q D Q D Q D Q D Q
D Q
D Q
D Q
D Q
D Q
D Q
DO3
DI4
D Q D Q D Q D Q D Q
D Q D Q D Q D Q D Q
D Q
D Q
D Q
D Q
D Q
D Q
DO4
DI5
D Q D Q D Q D Q D Q
D Q D Q D Q D Q D Q
D Q
D Q
D Q
D Q
D Q
D Q
DO5
DI6
D Q D Q D Q D Q D Q
D Q D Q D Q D Q D Q
D Q
D Q
D Q
D Q
D Q
D Q
DO6
DI7
D Q D Q D Q D Q D Q
D Q D Q D Q D Q D Q
D Q
D Q
D Q
D Q
D Q
D Q
DO7
ONE LUT
OUTPUT
DATA
BYTE
Single and Dual Port LUT RAM
Dual Port Distributed SRAM Detail
Cascading LUTs for Depth
Virtex 5 32 X 2
Dual Port LUT RAM
Virtex 5 32 X 6
Dual Port LUT RAM
Dual Port Select RAM FIFO
Counter Structure
Asynchronous FIFO Issues
• Problems with separate clock domains
– Speed discrepancy between the two domains
– Possibility of overflowing
• Arrival rate/departure rate problem
• Status communication
– Glitching conditions on counters
– Metastability
• Would like nice, tidy “always works” solutions
• Full details in Sunburst Design writeup by
Cummings & Alfke
Asynchronous FIFO Control
Virtex Family BRAMS
Family
Process
Virtex
32 K
4096
2048
1024
512
256
250 nm
X 1
X 2
X 4
X 8
X 16
Virtex E/EM
180 nm
X 1
X 2
X 4
X 8
X 16
Virtex II
150 nm
X1
X2
X 4
X 9
X 18
X 36
Virtex II Pro
130 nm
X1
X2
X 4
X 9
X 18
X 36
Spartan 3/E
90 nm
X1
X2
X 4
X 9
X 18
X 36
Virtex 4
90 nm
X1
X2
X 4
X 9
X 18
X 36
Virtex 5
65 nm
X2
X4
X 8
X 9
X 18
X 36
X1
16 K
8K
256 X 16 BRAM Module
DOUT 0-15
EN DATAOUT
ADDRESS
ADDR 0-7
RD
256 X 16 WR
CLK
DATAIN
DIN 0-15
256 X 32 BRAM Module
DOUT 16-31
DOUT 0-15
EN DATAOUT
RD
256 X 16 WR
ADDR 0-7
ADDRESS
ADDRESS
ADDR 0-7
EN DATAOUT
256 X 16 WR
CLK
DATAIN
DIN 0-15
RD
CLK
DATAIN
DIN 16-31
512 X 16 BRAM Module
Comment: slide needs
Inverter on one of the EN’s
DOUT 0-15
ADDRESS
ADDR 0-7
EN
DATAOUT
RD
256 X 16 WR
CLK
DATAIN
ADDR 0-7
EN
DATAOUT
ADDRESS
ADDR 8
256 X 16 WR
CLK
DATAIN
DIN 0-15
RD
BRAM Specialized Interconnect
DECODER
CKB WEB ENB
DIB0-7 DOB0-7
ADB0-7
DIA0-7 DOA0-7
ADA0-7
CKA WEA ENA
DECODER
DOUTB DOUTA
BRAM Output Multiplexing
Memory Array
1
2
4
DA[31-0]
DA[31-0]
DA[31-0]
0 - 35
0 - 35
0 - 35
0 - 35
DB[31-0]
DB[31-0]
DB[31-0]
1
2
4
36
36
Port A
9
18
DA[31-0]
DB[31-0]
PA[3-0]
PB[3-0]
DA[31-0]
DB[31-0]
PA[3-0]
PB[3-0]
DA[31-0]
DB[31-0]
36
PA[3-0]
PB[3-0]
Port B
9
18
36
BRAM/Multiplier Relationship
Virtex II BRAM Approach
16 Bit SRAM Structure
A1
Row Address Decoder
A0
A2 Column
A3 Address
Decoder
ENA
WE
OE
Control
Logic
DATA IN
DATA OUT
Single Storage Cell of SRAM
Storage
Cell
Row Address
Left Row (LR)
Transistor
Right Row (RR)
Transistor
From Column
Transistors
Single Bit SRAM Read/Write
Circuits
A1
Row Address Decoder
A0
Left Row (LR)
Transistor
Left Column (LC)
Transistor
Right Row (RR)
Transistor
Right Column (RC)
Transistor
A2 Column
A3 Address
Decoder
ENA
WE
OE
Control
Logic
DATA IN
DATA OUT
16 Bit Dual Port BRAM Structure
Row Address Decoder
A1
Row Address Decoder
A0
B0
B1
Column B2
Address B3
Decoder
A2 Column
A3 Address
Decoder
ENA
WE
OE
Control
Logic
DATA IN A
DATA OUT A DATA OUT B
DATA IN B
Control
Logic
ENA
OE
WE
512 X 36 Bit FIFO
Virtex 4 BRAM Symbol
V4 BRAM Output Register
Structure
V4 BRAM Cascading Structure
Virtex 4 FIFO Support Structure
(this stuff is inside the V4 BRAM module, built in)
8K X 4 Virtex 4 FIFO
Cascading like this requires a 2 IN NOR be built in the LUT fabric
512 X 72 Virtex 4 FIFO
Cascading like this needs 2 AND, 2 OR and 2 Inverters in LUT fabric
Virtex 5 Dual Port
BRAM Symbol
Virtex 5 BRAM
Organized X 64
Virtex 5 BRAM Configurable
Options
Virtex 5 BRAM Cascade
V5 BRAM Output MUX/Cascade
Circuitry
Timing with/without Fall Through
V5 BRAM 64 Bit ECC
Virtex RAM Closing Comments
• RAM may be the primary on board feature
beyond fabric of general use
• Makes having other on board resources more
effective
–
–
–
–
FIFOs –fast cross clock domain interfacing
Microprocessors – code/data storage
DSPs – on chip operand storage
And so on . . .
• See XAPP 463 (appendix) for Verilog/VHDL
code listing for using BRAM structure.