Transcript Multi-Gate technology - Advanced Silicon Device and Process Lab

Advanced Multi-Gate Technologies
for the Sub-25 nm Regime
黃
思
維
F90943078
Graduate Institute of Electronics Engineering
National Taiwan University
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Conventional Planar Bulk MOSFET
Challenges for Planar Bulk MOSFETs Scaling
Gate Leakage Current
Packing Density
Drive Current
Short Channel Effect (SCE)
Drain Induced Barrier Lowing (DIBL)
Device Scalability
Process Complexity
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Advantages of Non-Planar MOSFET
Ultra-Thin Body (UTB) Structure
Current Driven by Multi-Gate
Excellent Short-Channel Behavior
Better Gate-to-Channel Controllability
Reduced DIBL
Potential Scalability
CMOS-compatible Process
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Non-Planar MOSFET

Device Evolution of
Non-Planar MOSFETs

Dimension Restriction
of
Non-Planar MOSFETs
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Thickness of Si Body Tsb
UTB-SOI
DST
FinFET
-FET




Tsb ≤ 1/3 Lg
Tsb ≤ 1/3 Lg
Tsb ≤ 2/3 Lg
Tsb ≤ Lg
Szu-Wei Huang, C-V Lab, GIEE of NTU
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FinFET with 10-nm Gate Length
Layout and Process Flow
Fabricated with
(110) Orientation
to Enhance Hole
Mobility

Szu-Wei Huang, C-V Lab, GIEE of NTU
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FinFET with 10-nm Gate Length
Cross-section and Top View
Tox = 17 Å
Tsb :
17~26 nm
Double Gate Device
Szu-Wei Huang, C-V Lab, GIEE of NTU
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FinFET with 10-nm Gate Length
Electrical Characteristics
WCH = 2  Hfin
Szu-Wei Huang, C-V Lab, GIEE of NTU
SCE Reduced Due to :
Thicker Tsb
Dual Gate Structure
Abrupt S/D Junction
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FinFET with 10-nm Gate Length
Carrier Mobility on (110) Orientation
Field in Inversion Layer 
Hole Mobility 
(110) Crystal Orientation
Szu-Wei Huang, C-V Lab, GIEE of NTU
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FinFET with 10-nm Gate Length
CMOS-FinFET Inverter
Szu-Wei Huang, C-V Lab, GIEE of NTU
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FinFET with 10-nm Gate Length
Device Performance
Double Gate
NMOS
PMOS
Lg (nm)
10
Tsb (nm)
17~26
VDD (V)
1.2
Tox (Å)
17
Id (µA/µm)
446
356
Swing (mV/dec)
125
101
DIBL (mV/V)
71
120
Gate Delay (ps)
0.34
0.43
Szu-Wei Huang, C-V Lab, GIEE of NTU
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-FET with 25-nm Gate Length
Triple-Gate Device Structure
Gate Extension
Under Si Body
Decreasing Drain-Induced-Barrier-Lowing
Increasing Gate-to-Channel Controllability
Szu-Wei Huang, C-V Lab, GIEE of NTU
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-FET with 25-nm Gate Length
Cross-Section View
Tox = 17~19 Å
Tsb = 25 nm
HSi = 55 nm
Tsb 
Shielding Electrical Field from Drain
Reducing Parasitic Resistance
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-FET with 25-nm Gate Length
Characteristics of |VD|=1V Version
WCH = 2  Hfin + Tsb
Szu-Wei Huang, C-V Lab, GIEE of NTU
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-FET with 25-nm Gate Length
Characteristics of |VD|=0.7V Version
WCH = Hfin
Szu-Wei Huang, C-V Lab, GIEE of NTU
Gate Delay (ps)
NMOS
0.39
PMOS
0.88
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-FET with 25-nm Gate Length
Gate Delay Comparison of |VD|=0.7V Version
Gate Delay is Defined as ( CV/I )
Szu-Wei Huang, C-V Lab, GIEE of NTU
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-FET with 25-nm Gate Length
Demonstration of Multiple CMOS -FET Circuit
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Comparison of Device Geometry
If Channel Length = Lg
H
UTB-SOI ≤1/3Lg
W

FinFET

≤2/3Lg
-FET
≥2Lg
Lg
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Process Refinements of FinFET
Hydrogen Annealing
Higher Surface Quality
Improved Drive Current
Lower Gate Noise
Metal Gate Engineering
Ideal Mobility
Lower Gate Leakage Current
Higher Transconductance
Competitive ION/IOFF Ratio
Adjustable Vt
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Hydrogen Annealing
Increased Surface Si Migration Rate
Red Circle:
Improved
Line Edge
Roughness
Blue Circle:
Improved
Sidewall
Roughness
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Hydrogen Annealing

NMOS Drive Current
is More Degraded
Due To the Closer
Inversion Charge
Centroid of Electrons
Increased Current Due
To Decreased Surface
Trap Density

Szu-Wei Huang, C-V Lab, GIEE of NTU
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Hydrogen Annealing
Equivalent Gate Voltage Noise SVG
SVG=Output Drain Current Noise/Transconductance
Hydrogen Annealing Forms High Quality Surface
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Hydrogen Annealing
Carrier Mobility on the (110) Orientation
Mobility Degradation Due to Surface Roughness
Scattering µSR1/(Eeff Δ)2, where Δ is the RootMean-Square Value of Surface Roughness
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Metal Gate Engineering
Molybdenum-Gated FinFET
Gate Work Function for FDSOI CMOS
FinFET Technology is 4.4-5.0 eV.
Molybdenum Gate
A work Function of ~5V which is
suitable for p-FinFET
Nitrogen Implanted into Molybdenum
Followed by Annealing Results in Work
Function of ~4.4V which is suitable for
n-FinFET
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Metal Gate Engineering
Molybdenum-Gated FinFET
Nitrogen was
implanted at a
tilt of 60O
Szu-Wei Huang, C-V Lab, GIEE of NTU
Poly-Silicon was
used to prevent
oxidation and ion
channeling
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Metal Gate Engineering
Molybdenum-Gated FinFET

40 nm Mo Gate with
400 nm cap Poly-Si
Szu-Wei Huang, C-V Lab, GIEE of NTU
Mo Gate was
etched by Cl2
and O2 plasma

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Metal Gate Engineering
Molybdenum-Gated FinFET
PVD Mo is discontinuous due to the undercut
of buried oxide caused by over-etching by HF
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Metal Gate Engineering
Molybdenum-Gated FinFET
Multi-Vt is observed
by nitrogen
implantation
Szu-Wei Huang, C-V Lab, GIEE of NTU
Gate work Function
was changed by
nitrogen implantation
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Metal Gate Engineering
NiSi-Gated FinFET
(110) Orientation
NiSi Gate
CoSi2 Raised S/D
Lg = 100 nm
Tsb = 25 nm
Tox = 16 Å
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Metal Gate Engineering
NiSi-Gated FinFET
W = 2 Hfin
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Metal Gate Engineering
NiSi-Gated FinFET
10% Gm Gain achieved by the
elimination of Poly-Depletion Effect
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Metal Gate Engineering
NiSi-Gated FinFET
Gate Leakage of NiSi-Gated FinFET
is Lower than Poly-Si-Gated FinFET
Szu-Wei Huang, C-V Lab, GIEE of NTU
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Conclusion
10 nm CMOS FinFET and 25 nm CMOS -FET have
been successfully fabricated.
Excellent SCE and DIBL and other electrical
characteristics of both FinFET and -FET are obtained.
CMOS circuit for both 10 nm CMOS FinFET and 25
nm CMOS -FET are demonstrated.
Hydrogen annealing has verified to smoothen the line
edge and sidewall surface roughness, in which the
mobility and the gate noise are therefore improved.
The gate work function has shown to be adjusted by
using the metal/silicide gate to acquire desired device
properties.
Szu-Wei Huang, C-V Lab, GIEE of NTU
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References
[1] J. Kedzierski, et al, “Metal-gate FinFET and fullydepleted SOI devices using total gate silicidation,”
IEDM Tech. Dig., 2002, pp. 247-250.
[2] B. Yu, et al, “FinFET Scaling to 10 nm Gate Length,”
IEDM Tech. Dig., 2002, pp. 251-254.
[3] F.-L. Yang, et al, “25 nm CMOS Omega FETs,”
IEDM Tech. Dig., 2002, pp. 255-258.
[4] Y.-K. Choi, et al, “FinFET Process Refinements for
Improved Mobility and Gate Work Function
Engineering,” IEDM Tech. Dig., 2002, pp. 259-262.
Szu-Wei Huang, C-V Lab, GIEE of NTU
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