Transcript ModelSim_Seminar
VHDL & ModelSim
CPU Architecture
Serge Karabchevsky
Objectives
Course Website, Software and Hardware Logic Timing Introduction to VHDL ModelSim Simulation First Assignment Definitions
Course Website
http://hl2.bgu.ac.il
Announcements Assignments Lectures Forums Anyone can ask Anyone can answer (if he knows the answer) Check Google before asking at forum.
Reception hours At the forums Monday 16 00 -17 00 - Scheduling by email Email : [email protected]
Course Software
Modelsim (Simulator) http://model.com/content/modelsim-pe student-edition-hdl-simulation Quartus (FPGA Compiler) http://www.altera.com/products/software/quart us-ii/web-edition/qts-we-index.html
MARS (MIPS compiler) http://courses.missouristate.edu/KenVollmar/ MARS/
Course Hardware Altera DE1 FPGA Board
Cyclone II EP2C20F484C6 FPGA 50MHz,27MHz and 24MHz oscillators 4 pushbutton switches 10 toggle switches 10 red LEDS 8 Green LEDs
Logic Timing
Tpd : Time from state change at input to state change at output In Out t t
t pd
DFF Timing
Tco : Time from clock rise to output state change Tsu : Time that input must be stable before clock rise Th : Time that input must be stable after clock rise
t setup t hold
D SET
Q
CLR
Q
Clk In Out t t t
t co
Calculating Frequency
Long Path Rule (Setup): 1/F Max = Tco 1 +Tpd Max +Tsu 2 +t skew Short Path Rule (Hold): Tco 1 +Tpd Min > Th 2 +t skew
FF (Tco 1 ,Tsu 1 ,Th 1 ) Logic (Tpd) FF (Tco 2 ,Tsu 2 ,Th 2 ) CLK t skew
Introduction to VHDL
V ery high speed integrated circuits H ardware D escription L anguage Entities Architectures Structural Dataflow Behavioral (Process , examples) Test Bench Generic Variables Generate Loops Packages and Simulating Delays
VHDL Design
Design must have a top level entity with : At least one input (test-bench is an exception) At least one output (test-bench is an exception) Optional Parameter (generic variable) Each entity is located in separate file File is with .VHD extension
VHD File Structure
-- Library Definition library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -- Entity Definition entity counter is port (clk : in std_logic; q : buffer unsigned (7 downto 0)); end entity; -- Architecture Definition architecture rtl of counter is -- Component and signal declaration Begin -- Design Body process (clk) begin if (rising_edge(clk)) then q <= q + 1; end if; end process; end rtl;
An Entity
In the Entity we define our design like a black-box with only inputs and outputs.
entity
entity_name
is generic (
generic_declarations
) ; port (
port_declarations
end
entity_name
; ) ; entity
nand2
is port (
a,b : in std_logic; c : out std_logic
) ; end
nand2
; a b entity
xor
is generic (
N : integer := 4
) ; port (
a : in std_logic_vector(N-1 downto 0); b : out std_logic
) ; end
xor
; a(0) a(1) a(2) a(3) c c
Architecture
In the Architecture we define the logic of our Entity (contents) and it’s connection to inputs and outputs The types of architecture are : •
Structural
•
Dataflow
•
Behavioral architecture
architecture_name
of
entity_name [ component declaration ]
is
[ signal declaration ]
begin
[ design logic ]
end
architecture_name
; architecture
rtl
of
nand2
is begin c <= a NAND b; end
rtl
; a b c
Entity and Architecture
Architecture Signal Component Component
Entity
Process Signal Data Flow
Structural Architecture
Using existing components (entities) in order to build a new one, like connecting chips each to other All the components must be declared before the architecture begin Then the components are instantiated and connected each to other using signals
Structural AND Gate from NAND and NOT
c a b
entity
and2
is port (
a,b : in std_logic; c : out std_logic
) ; end
and2
; architecture
struct
of
and2
component
nand2
is is port (
a,b : in std_logic; c : out std_logic
end U1 : nand2 port map (a=> a ,b=>b, c=> nand_out); U2 : not_gate port map (a=> nand_out ,b=>c);
struct
; ) ; end component ; component
not_gate
is port ( end component ; signal nand_out : std_logic; begin
a : in std_logic; b : out std_logic
) ;
Data Flow Architecture
Circuits are described by indicating how the inputs and outputs of built-in primitive components (ex.
and
gate) are connected. In other words we describe how signals flow through the circuit.
r
entity latch is port ( s,r : in std_logic; q,nq : out std_logic ); end latch ; architecture dataflow begin q <=r nor nq; nq <=s nor q; end dataflow ; of latch is
s q nq
Behavioral Architecture
Describes the behavior of components in response to signals.
Behavioral descriptions of hardware utilize software engineering practices to achieve a functional model. Timing information may be included for simulations.
Requires PROCESS statement
What can be behavioral
Combinational Logic Simple combinational logic Latches Sequential logic Flip Flop Mix of Combinational logic with Flip-Flops Flip Flops with asynchronous Reset/Preset Test Bench
It is Not a Software
Behavioral description describes a Logic , not a software. Be careful of what you are writing.
Timing commands can be used only in test bench or for delays definition in simulation.
Do not use timing commands to create logic The design should work normally if you remove the timing commands
Process
Used for all behavioral descriptions Statements within a process are executed sequentially All processes in a VHDL description are executed concurrently Will be executed (in simulator) in case of state change of at least one signal in sensitivity list
PROCESS (
sensitivity list
)
declarations
BEGIN
Process body (behavioral description)
END PROCESS;
Signals
SIGNAL
a
,
b
:
std_logic
;
Signals are local for specific architecture , they are used for interconnect between different processes and components When assigning a signal in a process it will change only after process completion Only the last assignment counts (including assignments under IF or CASE) If there is no active assignment , signal holds it’s previous state ( Latch ) Assignment is done by ‘<=‘
Variables
Local to the process they are defined A variable behaves like you would expect in a software programming language Assignment takes time immediately Assignment is done by ‘:=‘
VARIABLE
tmp
:
integer range 0
TO
15
;
Combinational Description
All the process input signals must be in the sensitivity list Signal must have an active assignment in all the paths (if , case …). Otherwise latch will be created A default assignment can be used at the beginning of the process to avoid latches
Combinational Description Example
S[1..0] Equal1 2' h1 - A[1..0] B[1..0] EQUAL Equal0 OUT 2' h0 - A[1..0] B[1..0] OUT EQUAL I2[2..0] I1[2..0] I0[2..0] O~[2..0] DATAA SEL DATAB OUT0 MUX21 O~[5..3] DATAA SEL DATAB OUT0 MUX21 O[2..0]
Common Error
S[1..0] Equal1 2' h1 - A[1..0] B[1..0] OUT EQUAL Equal0 2' h0 - A[1..0] B[1..0] EQUAL Equal2 OUT 2' h2 - A[1..0] B[1..0] OUT EQUAL I2[2..0] I1[2..0] I0[2..0] 0 1 O[2]~4 0 1 O[1]~2 O[2]~7 0 1 O[2]~6 0 1 O[1]~3 0 1 O[0]~1 O[2]$latch D PRE Q ENA CLR O[1]$latch D PRE Q ENA CLR O[0]$latch D PRE Q ENA CLR 0 1 O[0]~0 O[2..0]
Sequential Description
rising_edge statement must present in the process body d1 d2 clock q~0 q~reg0 D PRE Q ENA CLR q
Asynchronous reset paths
Only one synchronous path Only one Asynchronous path clear clock Add0 8' h01 - A[7..0] B[7..0] OUT[7..0] ADDER Q[7..0]~reg0 PRE D Q ENA CLR Q[7..0]
Test Bench
Used to test the design functionality Not translated to real hardware Wraps around the design You can write everything you want (like Software)
Design Top Level Test Bench
Input generation
How Test Bench Works
DUT Output =?
observation Error Report Golden Model Golden Output Error Reporting : process(clk) begin if (clk'event and clk='1') then ASSERT out_dut = out_golden REPORT “Test Failed" SEVERITY error; end if; end process;
Generic variables
Compilation Driven Parameters Can’t change at run time
entity
nand2
is generic (tpd: time); port (
a,b : in std_logic; c : out std_logic
end
nand2
; ) ; architecture
rtl
of
nand2
is begin c <= a NAND b after tpd ; end
rtl
; Instantiation : U1: nand2 generic map ( tpd => 1ns ) port map (a => a_signal, b=>b_signal , c=>c_signal);
Generate loops
entity register is port( reset, clk: in std_logic ; d: in std_logic_vector (4 downto q: out std_logic_vector (4 downto 0); 0)); end register ; architecture struct of register is component dff port( reset, clk, d : in std_logic; q, q_not : out std_logic); end component ; begin Array_Of_DFFs: for i in D'range generate dffi: dff port map( reset => reset, clk => clk, d => d(i),q => q(i) ); end generate; end struct ; Data Clk Reset 5 D R Q 5 Q Data Clk Reset
clk
D Q R Q Data
D 4 D 3 D 2 D 1 D 0
D Q
Q 4
R D Q Q
Q 3
R D Q Q
Q 2
R D Q Q
Q 1
R D Q Q R Q
Q 0 reset
Packages
Saves time on component declaration , no need for code duplication.
sample_package.vhd
library IEEE; use IEEE.STD_LOGIC_1164.ALL; PACKAGE sample_package is component nand2 port(a,b : in std_logic; c : out std_logic); end component ; component not_gate port(a : in std_logic; b : out std_logic); end component ; end sample_package; In design files add :
use WORK. sample_package.ALL;
Simulating Delays
architecture
rtl
of
and2
begin c <= a and b after is 1ns; end
rtl
;
Creating component delay for simulation In The Test bench : a <= ‘1’, ‘0’ after 2 ns, ‘1’ after 7 ns; b <= ‘1’, ‘0’ after 4 ns, ‘1’ after 6 ns; All the times are relative to zero (Start of line execution) a c b 0 1 2 3 4 5 6 7 8 9 t[ns [ t[ns [ t[ns [
ModelSim Simulator
Learn By Example
First Example
N Bit Register Uses Package Download it from HL and simulate Are there any logic delays?
N N D Q Clk Reset
How to use ModelSim?
Create Project with “work” library ( “File->New->Project”) Add files to project ( “Project->Add to Project”) Edit .vhd files
Set compilation order
( “Compile->Compile order”)
Compile
all the .vhd files ( “Compile->Compile All”)
Load
the “test bench”
configuration
file. (double-click on the configuration link of the complied test bench in “work” library) Add a new wave window ( “View->New Window->Wave”)
How to use ModelSim? (cont ’)
Copy the relevant signals to the wave window Run simulation
(Simulate->Run->Run)
Work the right way … so u won’t loose grade: Change signal names to friendly ones
(Display Names)
Use “Dividers” between signals Mark time periods Zoom on the right signals Use Hexadecimal notations when necessary Save the wave format to use it later
( “File->Save
)
Second Example
Delay Line Download it from HL and run on your own.
Are there any logic delays?
Input N D Clk Clk Reset Q N D Clk Reset Q N N D Clk Reset Q N Output
Make Changes on the Second Example
Change clock period to 20n Change delay line depth to 4 Run the simulation again