Transcript Lecture_18_Test_SRAM_40

Weak SRAM Cell Fault Model
and
a DFT Technique
Mohammad Sharifkhani,
with special thanks to
Andrei Pavlov
University of Waterloo
Outline
 Background and motivation
SRAM issues: noise, SNM, weak cells
 SRAM SNM sensitivity analysis
vs. process variation
vs. non-catastrophic defect resistance
vs. operating conditions
 Programmable weak SRAM cell fault model
 DFT for weak cell detection
Detection concept
Implementation
 Conclusions
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Noise Sources
Static
Dynamic
 Process offsets and
mismatches
 Cross-talk
 Operating conditions
variations
 -particles
 Ripples in power rails
Most of dynamic sources are quasi-static
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What is SNM?
SNM = max static
noise, which can be
tolerated by an
SRAM cell without
changing its logical
state
D
SNM 
2
v
y
D
SNM
D
D
450
x
D
u
Seevinck et al, JSSC’87
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What is a weak SRAM cell?
Vnode B
VDD
BL
WL
BLB
load-1
load-2
Let’s consider
a standard
A SRAM cell:B
6T
access-1
driver-1
access-2
driver-2
SNMtyp
Vgood
VDD
Vnode A
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What is a weak SRAM cell?
Vnode B
VDD
Weak cell = a cell with
inadequate SNM that can be
easily flipped
Vweak
SNMweak
Vgood
SNMtyp
VDD
Vnode A
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Why Test Weak SRAM Cells?
Because weak SRAM cells:
 Prone to stability faults
 Manifest reliability problems
 Can signify defects, which…
 Escape regular march tests
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What Does SNM Depend On?
 Process variation (mismatch / offset):
VTH spread
LEFF, WEFF spread
 Resistance of non-catastrophic defects:
RBREAK
RBRIDGE
 Operation conditions:
VBL
VDD
VWL
T0C
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Static Noise Margin
as a Function of Process Variation
all results for 0.13um technology,
read-accessed cell,
i.e. VWL=VBL=VDD
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SNM vs. VTH (Single Transistor)

Typical process
corner

SNM=100% @ zero
VTH deviation

Driver  strongest
impact, load 
weakest impact
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SNM vs. VTH (Single Transistor)

Typical + slow
process corners

For slow:
SNM>100% @ zero
VTH deviation
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SNM vs. VTH (Single Transistor)

Typical + slow +
fast process
corners

For fast:
SNM<100% @
zero VTH deviation
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SNM vs. VTH (Multiple Transistors)

Typical process
corner

One VTH changes,
while some other
are biased

Strong SNM
decline for some
VTH combinations
(at max asymmetry)
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SNM vs. Leff and Weff (Single Transistor)

SNM=100% for
typical geometry

Geometry
variations – weak
impact on SNM
(max 7%)
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Static Noise Margin
as a Function of Non-Catastrophic
Defect Resistance
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SNM vs. Break Resistance

 Rbreak  SNM

SNM vs. gate
breaks  weak
dependence

SNM vs. driver
breaks  strong
dependence
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SNM vs. Bridge Resistance

 Rbridge 
SNM

SNM vs. Rbridge 
uniform
dependence
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Static Noise Margin
as a Function of Operation
Conditions
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SNM vs. Bit Line Voltage

Typical process

If VBL>0.8V 
SNM=100%

If VBL<0.35V 
SNM=0% - hard
failure ( normal write)

If 0.35V<VBL>0.8V
 SNM linearly 
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SNM vs. Bit Line Voltage

Typical + slow
process corners

VBL>0.8V 
SNM>100%

VBL<0.35V 
SNM=0% - hard
failure (or normal
write)

0.35V<VBL>0.8V 
SNM linearly 
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SNM vs. Bit Line Voltage

Typical + slow +
fast process
corners

VBL>0.8V 
SNM<100%

VBL<0.35V 
SNM=0% - hard
failure (or normal
write)

0.35V<VBL>0.8V 
SNM linearly 
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SNM vs. Global VDD

Typical + slow +
fast process
corners (extreme
cases)

SNM linearly 
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SNM vs. Local VDD

Local  resistive
break in local VDD

Typical + slow +
fast process
corners (extreme
cases)

@VDD_LOCAL<0.8V
SNM=0

@VDD_LOCAL>0.8V
SNM linearly 
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SNM vs. Word Line Voltage

Typical process

Read-accessed
SRAM cell (SNM
deviation @VWL=VDD0%)

@VWL <VTH_ACCESS
SNM=max

@VWL >VTH_ACCESS
SNM linearly 
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SNM vs. Word Line Voltage

Typical + slow
process corners
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SNM vs. Word Line Voltage

Typical + slow +
fast process
corners
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SNM vs. Temperature

Weak
dependence

10% max (fast )

2.5% min (slow)
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Proposed Weak Cell Fault Model
and a Programmable DFT
Technique
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Weak cell fault model

SNM vs. nodenode R

@Rnode-node
[50k,500k] –
linear
dependence
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Weak cell fault model
BL
BLB
WL
• Resistor between
nodes A and B
node A
node B
• Which is equivalent to
• Negative feedback for
inverters of an SRAM
node A
node B
cell
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Programmable detection concept
Vnode B
VDD
Vweak
SNMweak
Vgood
SNMtyp
VDD
Vnode A
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Programmable detection concept
Vnode B
VDD
@ VTEST:
•weak cell flips
•good cell does not flip
Vweak
VTEST
Vgood
SNMweak
SNMtyp
VDD
Vnode A
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Proposed DFT concept
R
number of cells with state "0" in a set of
n cells
n
• Changing of ratio R
Vnode A
Vnode B
brings nodes to
different potentials
• Weak cell will flip and
R=0
0.5
1
node voltage  R
will be detected
• Good cell will retain
data
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Proposed DFT Algorithm
START
write 0/1 ratio R
Ø
Ø
Ø
Ø
Ø
precharge
enable n WLs
short BLs
disable n WLs
release BLs
read n cells back
invert ratio R
select next
0/1 ratio
yes
more 0/1 ratios
to test?
no
1. Write background
ratio of zeroes and
ones
2. Normal precharge
3. Enable n word
lines
4. Right after that
short bit lines
5. Release word lines
6. Release bit lines
FINISH
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Word Line decoder
Proposed DFT Implementation
1. Write background
ratio of zeroes and
ones
WL1
WL2
WL3
2. Normal precharge
WD
WLn
3. Enable n word lines
WD logic
4. Right after that short
bit lines
WD
5. Release word lines
6. Release bit lines
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Proposed DFT Simulation Results
•
Rweak=200k
(~65% SNM)
•
Five “0”,
three ”1”
•
Weak cell is
detected!
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Proposed DFT Simulation Results
•
Rweak=200k
(~65% SNM)
•
Three “0”,
five ”1”
•
Weak cell is
not detected
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Proposed DFT detection capability
•
Rweak=100k500k
•
Five “0”,
three ”1”
•
Weak cell
flips for
Rweak<200k
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Conclusions
 Weak SRAM cells can escape march tests 
need DFT
 Cell stability is sensitive to process and
operation disturbances
 Weak cell fault model is essential in developing
test techniques
 Proposed DFT efficiently detects weak SRAM
cells, i.e. cells with inadequate SNM
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