Transcript TEM - CEA
In-line transmission electron microscopy for micro and nanotechnologies R&D V. Delaye, F. Andrieu, F. Aussenac, O. Faynot, R. Truche, C. Carabasse, A. L. Foucher, A. Danel CEA-LETI, MINATEC, 17 rue des Martyrs, 38054 Grenoble Cedex 9 France Phone: +33 (0)4 38 78 40 08 e-mail: [email protected] Inline TEM Dedicated Cleanroom Area FIB/SEM Dual beam : Introduction FEI Expida 1285 Advanced microelectronics, micro and nanotechnologies characterizations needs : Reduced cycle time (cost) High resolution imaging and analysis of materials and structures with nanometers dimensions An adapted tool is Transmission electron microscope (TEM), but : Dedicated for off-line laboratories Destructive Delicate and time consuming sample preparation To meet the needs of such R&D facility, as much in term of cycle time as resolution : Full 200 and 300 mm wafer FIB-SEM dual beam system for sample preparation (100 nm thick lamella) 200 kV TEM installed close to dual beam and inside cleanroom. 300 mm FOUP & 200 mm Open Cassette SEM column : Sirion (3 nm resolution) FIB column : Sidewinder (low kV thinning) Beam Chemistries: Tungsten deposition SiO2 deposition Insulator enhanced etch Nanolift option (TEM sample preparation & transfer): ChunkWizard - Omniprobe - TSU X-Ray Analysis (Oxford) TEM samples 200 & 300 mm wafers TEM : FEI Tecnai G² F20 STWIN TMP Sample transfer FIB sample preparation TEM analysis Voltage : 200 kV Electron Source : FEG TEM point resolution : 0.24 nm TEM line resolution : 0.14 nm STEM resolution : 0.20 nm 2kx2k GATAN CCD X-Ray Analysis (EDAX) In-line TEM resolution Wafer return for front-end levels The microscope supplier (FEI) specifications are all achieved in dedicated area except for 50Hz (60dB instead of less than 54 dB) acoustic level. However : Resolution tests in TEM and STEM modes have been successfully conduced with the FEI Tecnai S-Twin 200 kV microscope installed. An other major concern in R&D and manufacturing semiconductor industry is to reduce wafer costs due to destructive characterization. It has been already shown that sample preparation impact on wafer is limited to 1 mm around the FIB crater; such impact allows the industry (1) to re-introduce wafers after TEM sample extraction at back-end levels. D11 NMOSL1B D09 D10 depending on the sample size and the lamella thickness required. This flow includes : Electron beam assisted tungsten protective layer deposition to reduce surface damage to 1 nm instead of 30 nm with ion beam Low-kV (5kV) ion beam final thinning for less than 100 nm lamellas (nanometer gate oxide measurement for example) Die description with the 2 localized patterns Level Description Preparation to observation flow 200 Starting from wafer loading in the dual beam to TEM picture delivery : 7 A cycle time between 2h30 and 6h00 hours has been obtained Wafer mapping (11 e-beam dies) Step # 0.14 nm line resolution Step 1 After active area patterning 2 During gate stack formation 2 Before extension formation 2 W=0.07µm 300 µm from W=0.04µm W=0.05µm W=0.10µm 180 µm from W=0.05µm 405 µm from W=0.04µm W=0.04µm W=0.15µm Site location 360 µm from W=0.04µm W=0.03µm W=0.25µm 180 µm from W=0.04µm 405 µm from W=0.04µm Step 2 Step 3 SEM image from isolated PTGL250 transistors pattern with FIB crater zoom 11 12 01 & 03 01 PTGL250 NMOSL1B PTGL250 12 Vt PTGL250 NMOSL1B (same devices area) D04 04 < 500µm D05 Electrical test PTGL250 D01 (other devices area and dies) D03 > 500µm D02 Electrical test D08 Transistor D06 Die(s) D07 To go further, we made 2 samples extractions (common gate pattern NMOSL1B L=70nm and isolated transistor PTGL25 W=50nm) at 3 front-end process levels on two FDSOI (Fully Depleted SOI) wafers to study the impact on electrical performances. From a 12 wafers lot Dedicated TEM area inside the cleanroom : Anti-vibration TMC table Acoustical walls Adapted lighting conditions Adapted air conditioning flows Magnetic field canceling system Wafer (slot ) HR-STEM Si 110 Number of Lift-out HR-TEM Si 110 Vt NMOSL1B Electrical tests results -0,34 (1st analysis) 00:15; 10% 2 - Sample milling (5x5 µm) 00:15; 10% 8 -Transfer to TEM 00:15; 10% 3 - Lift out 7 - Capsule Unloading 00:05; 3% (sample extraction) 00:15; 10% 4 - Capsule Loading 00:05; 3% 6 - Thinning 00:40; 27% Chunk milling Probe welding Chunk lift-out The device extraction does not affect the electrical performance of all the devices further than 500 µm (from another pattern in the same die). On NMOSL1B common gate pattern, devices of the whole pattern are completely scrapped. PTGL250 transistors : Voltage threshold On PTGL250 isolated transistors other devices, from 180 to 400 µm, on the same pattern work (even if, with degraded performance) except for Step 2. This new result confirms the localized impact of a FIB extraction around the crater for advanced front-end levels. Min -0,42 VT -0,44 D01 -0,46 D03 -0,48 D04 -0,5 -0,52 -0,54 P1 1 TEM/STEM sample imaging and EDX protective layer) Max -0,4 FIB crater 5 - Sample transfer to TEM grid 00:10; 7% FDSOI Transistor 0,9 0,8 0,7 Max 0,6 Gm (µS/µm) 200 & 300 mm Lots wafers TEM sample preparation using FIB/SEM DualBeam 9 - First TEM Observation 00:30; 20% (inclunding : area of Interest localization and electron assisted W deposition -0,38 W =0 .0 P1 5µ 2 m W =0 P1 .0 5µ 1 W m =0 .0 P1 7µ 2 m W =0 .0 P1 7µ 1 m W =0 P1 .1 µm 2 W =0 P1 .1 1 µm W =0 .1 P1 5µ 2 m W =0 P1 .1 5µ 1 W m =0 .2 P1 5µ 2 m W =0 .2 5µ m 1 - Wafer loading -0,36 VT (V) 2h30 to 6h00 hours/sample Time management for a 5x5x0.1µm lamella Min 0,5 gm 0,4 D01 0,3 D03 D04 0,2 0,1 P1 1 W =0 .0 P1 5µ 2 m W =0 .0 P1 5µ 1 m W =0 .0 P1 7µ 2 m W =0 .0 P1 7µ 1 m W =0 .1 P1 µm 2 W =0 P1 .1 1 µm W =0 .1 P1 5µ 2 m W =0 .1 P1 5µ 1 m W =0 .2 P1 5µ 2 m W =0 .2 5µ m 0 PTGL250 transistors : Transconductance Conclusion : Transfer to grid Chunk approach Chunk view Thinned chunk FIB/SEM Metal gate No measured impact die to die Reduced impact within a pattern, but depending on following process step 200 and 300 mm wafers can be re-introduced within the process flow Applications : step by step analysis, process monitoring, defectivity. TEM ACKNOWLEDGMENTS : Sample preparation to observation flow example The authors would like to thank FEI Company for assistance and support. This work has been carried out, in the frame of CEA-LETI / ALLIANCE collaboration and STMicroelectronics. REFERENCE : (1) : BICAIS-LEPINAY N. and al., Proceedings of SPIE vol. 6152, 2006. www.leti.fr © CEA 2007. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA