Transcript A 600MS/s 30mW 0.13 µm CMOS ADC Array Achieving over 60dB

A 600MS/s 30mW 0.13µm CMOS ADC
Array Achieving over 60dB SFDR with
Adaptive Digital Equalization
• Time-interleaved ADC array
– High sampling rate, low power
– Channel mismatch errors
• Offset, gain, linearity and skew
• Approaches
– Correlation, statistics, and Chopping
• Slow convergence, involved analog path, ad-hoc solutions
– Equalization
• Fast convergence, digital post-processing, systematic solution
Equalization-Based Conversion
Architecture
V
Q
os
Analog
Chip 1X
Ref.
ADC Dr
Software
CN-1
C1
C0
dN-1
d1
d0
Фr(599.4KHz)
ADC1
Vin
D1
ADF1
Ф1(60MHz)
T/H
+VR
-VR
Vin
X
C0
SAR
Logic
D
Vin N-1 C j
Din =
=
  2d j -1 +Dos + QN
VR j=0 Ctot
1X
Ф (600MHz)
ADC10
Ф1
...
DLL
Ф10
D10
Ф10(60MHz)
ADF10
Channel mismatch errors
automatically eliminated w/
equalization !
Performance Summary
1.1 mm
70
BIAS
THAs
ADC
1-10
60
1.0 mm
DLL
REF
ADC
SNDR / SFDR [dB]
REF CLK
SNDR w/o calibration
SNDR w/ calibration
SFDR w/o calibration
SFDR w/ calibration
50
40
30
fs = 600 MS/s, Ain = 0.9 FS
20
0
Ours
ISSCC 06
ISSCC 08
VLSI 08
100
200
300
400
500
input frequency [MHz]
600
700
Process
(µm)
fs
(MS/s)
SFDR
(dB)
SNDR
(dB)
Power
(mW)
FOM
(pJ)
0.130
0.130
0.065
0.065
600
600
250
800
65.2
43
48
58
47.3
33.1
28
47.8
23.6
5.3
1.2
30
0.21
0.22
0.24
0.28
800