Transcript Hierarchical Power Gating

Use of Hierarchical Design Methodologies in
Global Infrastructure of the POWER7+
Processor
Brian Veraa ([email protected])
Ryan Nett ([email protected])
Ryan Kruse ([email protected])
© 2013 IBM Corporation
Introduction

POWER7+ Microprocessor
– 567mm2
– 2.1B devices at 4+GHz core frequency
– Large global design team

Hierarchical implementation
– Divide and Conquer

Certain global structures span hierarchy
– Power
– Clock
– I/O

We will discuss unique PD challenges presented by these structures
– Over/Under booking physical resource
– Connectivity across hierarchy
– Floorplanning around these structures
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Example of POWER7+ Hierarchy
POWER7+ Chip
Core + Cache
Load/Store Unit
Core
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Global Infrastructure (G.I.)
 Implemented at top level of hierarchy
– Clock Distribution
– Power Distribution
– I/O connections
 Load/Store Unit example
– First design team delivers LSU
– Second design team implements clock distribution at top level
– Third design team implements power gating at top level
– Many G.I. components fall within physical perimeter of child
 Challenge: Communicate physical design data across hierarchy
Clock
buffers
Load/Store Unit
(great-grandchild of chip)
Power
gating
circuits
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Communicating PD data across hierarchy: Parent Covers
Generate new
G.I. abstract
Parent
Child feeds back
change
proposals to G.I.
owner
Parent Cover
Child1
Child2
Parent resolves
floorplan conflicts
Generate parent
cover for child
 Parent cover represents G.I. content interacting with child
 Feedback loop to resolve parent/child conflicts
 Used by child for
– Floorplanning
– Routing
– Checking
 Multi use children get unioned parent cover
Update child abstract
to reflect inverse of
parent cover
Child respects
parent cover during
floorplan and routing
Parent runs G.I.
 child collision
checking
Child runs LVS /
DRC
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Example of Parent Cover Assembly at Chip Level
Load/Store Unit (8 copies)
POWER7+ Chip
Union 8 copies
Chip level Power Gate circuits
Load/Store Parent Cover
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Challenges with Hierachical Design
 Over/Underbooking resource
 Connectivity Across Hierarchy
 Floorplanning around G.I. Content
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Overbooking and Underbooking
Parent
 To enable parallel design work, initial G.I. abstractions
are based on estimates
– Accuracy of estimates improves over time
Child1
Child2
 Overbooking
– Cost is suboptimal utilization
 Underbooking
– Cost is late design change
 Late changes to G.I. abstraction can drive floorplanning,
routing, and timing efforts at a schedule sensitive time of
the project
 The POWER7+ chip team generated parent covers
regularly throughout the design cycle to reflect higher
quality G.I. component abstracts as their designs
matured
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Connectivity Across Hierarchy
Power connections to G.I.
 Certain G.I. components need power connectivity to children
– Clock buffers are connected into child power grid
– Power gate circuit supplies power to children
• Power gate circuit inputs hidden from children
Power Path to clock circuits
Power Path through power gate circuits
Chip
via
via
metal
via
metal
via
metal
via
metal
Unit Circuits
Child Unit
Metal (power)
via
Metal (power)
via
metal
via
metal
via
metal
via
metal
Chip
via
via
metal
via
metal
via
metal
via
metal
Clock Buffer
Unit Circuits
G.I. Component
Child Unit
C4
via
metal
via
metal
via
metal
via
metal
via
metal
via
metal
via
via
metal
via
metal
via
metal
via
metal
Power gate circuit
G.I. Component
metal
metal
via
via
metal
via
metal
via
metal
via
metal
Unit Circuits
Child Unit
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Connectivity Across Hierarchy
Checking errors encountered in parent
V1
V2
Area where both V1 and V2 are
present in the parent  Short in
parent if child connects to it!
Parent
Inst 1 of
child
Unioned
shapes
GND
Inst 2 of
child
(x1,y1)
(x2,y2)
 Case 1: Child contacts V1/V2 pin
– Problem: LVS short between
V1 and V2 at parent level
– Solution: Represent V1/V2
union as blockage, not pins
GND exists in only 1 parent instance.
Potential DRC or LVS open if child
connects to it!
 Case 2: Child contacts GND pin to complete a
signal route
– Problem 1: LVS open at parent in Inst 2
– Problem 2: DRC error generated at parent in
Inst 2 (min area or notch)
– Solution: Don’t permit signal routes to contact
parent cover
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Connectivity Across Hierarchy
False checking errors encountered in child
Parent Cover
V1
V2
V1 (A)
V2
 Child contains two power rails: V1, V2
 G.I. content contains only V1
 Pin V1 (A) is connected to V1 grid by layout of G.I. component
 Child sees V1 (A) as an LVS open
 Checking in parent context is LVS Clean
 False opens are communicated to parent to refine parent cover
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Floorplanning Around G.I. Content
 G.I. circuits consumed a large amount of metal resource
– Influenced child floorplanning and route planning.
• Congestion analysis
– Floorplans were adjusted to minimize the number of flight-lines crossing a particular G.I.
component.
– In other cases the G.I. was altered.
 Consider grouping tightly coupled circuits on the same side of a G.I. component.
Load/Store Unit
© 2013 IBM Corporation
Conclusion
 POWER7+ relied on hierarchical methods to close a large design with a global design team
– Concurrent design and schedule closure
– Flat design of selected components to meet high performance needs
 Management of Global Infrastructure components required:
– Effective abstraction
– Connectivity modeling across hierarchy
– Careful floorplanning
 Newer generations of processors are likely to demand more global power and clock
management features
– More thorough G.I. planning and execution
– Better hierarchical interaction management
 Techniques and Tools developed by POWER7+ will continue to be leveraged in the future
© 2013 IBM Corporation