Transcript FQMS_Micro06_ioana - Computer Engineering Research Group

Fair Queuing Memory
Systems
Kyle Nesbit, Nidhi Aggarwal,
Jim Laudon*, and Jim Smith
University of Wisconsin – Madison
Department of Electrical and Computer Engineering
Sun Microsystems*
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Motivation: Multicore Systems

Significant memory bandwidth
limitations


Bandwidth constrained operating points
will occur more often in the future
Systems must perform well at
bandwidth constrained operating points

Must respond in a predictable manner
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Bandwidth Interference

IPC
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0.6
0.4
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Desktops
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Servers

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Soft real-time
constraints
Fair sharing /
billing
Decreases overall
throughput
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Solution

A memory scheduler based on



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First-Ready FCFS Memory Scheduling
Network Fair Queuing (FQ)
System software allocates memory system
bandwidth to individual threads
The proposed FQ memory scheduler
1. Offers threads their allocated bandwidth
2. Distributes excess bandwidth fairly
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Background


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Memory Basics
Memory Controllers
First-Ready FCFS Memory Scheduling
Network Fair Queuing
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Background
Memory Basics
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Micron DDR2-800 timing
constraints
tRCD
Activate to read
5 cycles
tCL
Read to data bus valid
5 cycles
tWL
Write to data bus valid
4 cycles
tCCD
CAS to CAS (CAS is a read or a write)
2 cycles
tWTR
Write to read
3 cycles
tWR
Internal write to precharge
6 cycles
tRTP
Internal read to precharge
3 cycles
tRP
Precharge to activate
5 cycles
tRRD
Activate to activate (different banks)
3 cycles
tRAS
Activate to precharge
18 cycles
tRC
Activate to activate (same bank)
22 cycles
BL/2
Burst length (Cache Line Size / 64
bits)
4 cycles
tRFC
Refresth to activate
51 cycles
tRFC
Max refresh to refresh
28,000 cycles
(measured in DRAM address bus cycles)
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Background:
Memory Controller
CMP
Processor
L1 Caches
Processor
L1 Caches
L2 Cache
L2 Cache
Memory Controller
SDRAM
Chip
Boundary
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Background:
Memory Controller

Translates memory requests into
SDRAM commands

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Tracks SDRAM timing constraints

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Activate, Read, Write, and Precharge
E.g., activate latency tRCD and CAS
latency tCL
Buffers and reorders requests in order
to improve memory system throughput
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Background:
Memory Scheduler
Processor Data Bus
Memory
Requests
Processor Data Bus
Arrival Time Assignment
Cache Line
Read Buffer
Transaction
Buffer
Bank 1
Requests
…
Bank n
Requests
Cache Line
Write Buffer
FR-FCFS Scheduler
SDRAM Address Bus
SDRAM Data Bus
SDRAM Data Bus
Data Path
Request / Command Path
Control Path
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Background:
FR-FCFS Memory Scheduler
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A First-Ready FCFS priority queues
1.
2.
3.
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Ready commands
CAS commands over RAS commands
earliest arrival time
Ready with respect to the SDRAM timing
constraints
FR-FCFS is a good general-purpose
scheduling policy [Rixner 2004]

Multithreaded issues
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Example: Two Threads
Bursty MLP, bandwidth constrained
a5a6a7a8
a1a2a3a4
Thread 1
Memory Latency
Computation
Isolated misses, latency sensitive
a1
a2
a3
a4
a5
Thread 2
Computation
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First Come First Serve
1a2a3 4
a
a
Thread 1
a5a6a7a8
Shared
Memory
System
Thread 2
a1
a2
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Background:
Network Fair Queuing
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Network Fair Queuing (FQ) provides QoS
in communication networks

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Routers use FQ algorithms to offer flows
their allocated bandwidth
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Network flows are allocated bandwidth on each
network link along the flow’s path
Minimum bandwidth bounds end-to-end
communication delay through the network
We leverage FQ theory to provide QoS in
memory systems
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Background:
Virtual Finish-Time Algorithm
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The kth packet on flow i is denoted
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pik virtual start-time
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pik
Sik = max { aik, Fik-1 }
pik virtual finish-time
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Fik = Sik + Lik / i
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i flow i’s share of network link
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A virtual clock determines arrival time aik
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VC algorithm determines the fairness policy
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Quality of Service

Each thread is allocated a fraction i of the
memory system bandwidth

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Desktop – soft real time applications
Server – differentiated service – billing
The proposed FQ memory scheduler
1.
2.
Offers threads their allocated bandwidth,
regardless of the load on the memory system
Distributes excess bandwidth according to the
FQ memory scheduler’s fairness policy
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Quality of Service

Minimum Bandwidth ⇒ QoS

A thread allocated a fraction i of the
memory system bandwidth will perform
as well as the same thread on a private
memory system operating at i of the
frequency
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Fair Queuing Memory
Scheduler
Thread 1
Requests

VTMS is used to
calculate memory
request deadlines

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Request deadlines are
virtual finish-times
FQ scheduler selects
1.
2.
the first-ready pending
request
with the earliest
deadline first (EDF)
Thread 1
VTMS
…
…
Thread m
Requests
Thread m
VTMS
Deadline / Finish-Time
Algorithm
Transaction
Buffer
FQ Scheduler
SDRAM
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Fair Queuing Memory
Scheduler
Thread 1 a1a2a3a4
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Virtual Time
Dilated latency
by the reciprocal
Memory
i
Shared
Memory
System
Thread 2
Deadlines
Deadlines
a1
a2
a3
a4
Virtual Time
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Virtual Time Memory System
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Each thread has its own VTMS to model its
private memory system
VTMS consists of multiple resources
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Banks and channels
In hardware, a VTMS consists of one register
for each memory bank and channel resource
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A VTMS register holds the virtual time the virtual
resource will be ready to start the next request
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Virtual Time Memory System
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A request’s deadline is its virtual finish-time
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The time the request would finish if the request’s
thread were running on a private memory system
operating at i of the frequency
A VTMS model captures fundamental SDRAM
timing characteristics

Abstracts away some details in order to apply
network FQ theory
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Priority Inversion


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First-ready scheduling is required to
improve bandwidth utilization
Low priority ready commands can
block higher priority (earlier virtual
finish-time) commands
Most priority inversion blocking occurs
at active banks, e.g. a sequence of
row hits
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Bounding Priority Inversion
Blocking Time
1.
2.
When a bank is inactive and tRAS
cycles after a bank has been
activated, prioritize request FR-VFTF
After a bank has been active for tRAS
cycles, FQ scheduler select the
command with the earliest virtual
finish time and wait for it to become
ready
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Evaluation
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Simulator originally developed at IBM
Research
Structural model
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Adopts the ASIM modeling methodology
Detailed model of finite memory system
resources
Simulate 20 statistically representative
100M instruction SPEC2000 traces
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4GHz Processor – System
Configuration
Issue Buffer
64 entries
Issue Width
8 units (2 FXU, 2 LSU, 2 FPU, 1 BRU, 1 CRU)
Reorder Buffer
128 entries
Load / Store Queues
32 entry load reorder queue, 32 entry store reorder queue
I-Cache
32KB private, 4-ways, 64 byte lines, 2 cycle latency, 8 MSHRs
D-Cache
32KB private, 4-ways, 64 byte lines, 2 cycle latency, 16 MSHRs
L2 Cache
512KB private cache, 64 byte lines,
Memory Controller
16 transaction buffer entries per thread, 8 write buffer entries per
thread, closed page policy
SDRAM Channels
1 channel
SDRAM Ranks
1 rank
SDRAM Banks
8 banks
8-ways, 12 cycle
latency, 16 store merge buffer entries, 32 transaction buffer entries
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Evaluation
Single Thread Data Bus Utilization
Utilization
100%
80%
60%
40%
20%
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We use data bus utilization to roughly
approximate “aggressiveness”
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Evaluation
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We present results for a two thread
workload that stresses the memory system
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IPC normalized to QoS IPC
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Construct 19 workloads by combining each
benchmark (subject thread) with art, the most
aggressive benchmark (background thread)
Static partitioning of memory bandwidth i = .5
Benchmark’s IPC on private memory system at
i = .5 the frequency (.5 the bandwidth)
More results in the paper
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FQ
FR-FCFS
1
0.5
Normalized IPC
1.5
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Normalized IPC
Normalized IPC of Subject Thread
Normalized IPC of Background Thread (art)
Throughput – Harmonic Mean of Normalized IPCs
1.4
Harmonic Mean of Normalized IPCs
FR-FCFS
FQ
1.2
1
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0.6
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Subject Thread of Two Thread Workload (Background Thread is art)
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Summary and Conclusions

Existing techniques can lead to unfair
sharing of memory bandwidth resources
⇒ Destructive interference
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Fair queuing is a good technique to provide
QoS in memory systems
Providing threads QoS eliminates
destructive interference which can
significantly improve system throughput
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Backup Slides
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Generalized Processor
Sharing
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Ideal generalized
processor sharing (GPS)
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Each flow i is allocated a
share i of the shared
network link
GPS server services all
backlogged flows
simultaneously in proportion
to their allocated shares
Flow 1
Flow 2
1
2
Flow 3 Flow 4
3
4
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Background:
Network Fair Queuing

Network FQ algorithms model each
flow as if it were on a private link

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Flow i’s private link has i the bandwidth
of the real link
Calculates packet deadlines

A packet’s deadline is the virtual time the
packet finishes its transmission on its
private link
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Virtual Time Memory System
Finish Time Algorithm

Thread i’s kth memory request is denoted

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mik bank j virtual start-time

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Bj.Fik = Bj.Sik + Bj.Lik / i
mik channel virtual start-time
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Bj.Sik = max { aik , Bj.Fi(k-1)’ }
mik bank j virtual finish-time


mik
C.Sik = max { Bj.Fik-1, C.Fik-1}
mik channel virtual finish-time
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C.Fik = C.Sik + C.Lik / i
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Fairness Policy
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FQMS Fairness policy: distribute excess
bandwidth to the thread that has consumed
the least excess bandwidth (relative to its
service share) in the past

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Different than the fairness policy commonly used
in networks
Differs from the fairness policy commonly
used in networks because a memory system
is an integral part of a closed system
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Background:
SDRAM Memory Systems
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SDRAM 3D Structure


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Banks
Rows
Columns
SDRAM Commands

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Activate row
Read or write columns
Precharge bank
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Virtual Time Memory System
Service Requirements
SDRAM Command
Bcmd .L
Ccmd .L
Activate
tRCD
n/a
Read
tCL
BL/2
Write
tWL
BL/2
Precharge
tRP + (tRAS - tRCD - tCL)
n/a


The tRAS timing constraint overlaps read and write
bank timing constraints
Precharge bank service requirement accounts for
the overlap
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