Transcript UML-VHDL
Application of UML
for Hardware Design
Based on Design Process Model
Authors: R. Damasevicius, V. Stuikys
Speaker: Prof. Vytautas STUIKYS,
Software Engineering Department,
Kaunas University of Technology,
Kaunas, Lithuania
E-mail: [email protected]
Phone: +370-37-300399
Content
Motivation
Higher-Level Abstractions: Design
Processes & UML-Based Specification
Taxonomy, Definition, Examples
Metamodel for Conversion of a given
Specification from UML to VHDL
Design Flow, Experiments
Evaluation, Discussion, Conclusions
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MOTIVATION
MAIN DESIGN PROBLEM (Complexity and its
derivatives - quality, productivity, time-to market)
can be solved through:
We INTRODUCE 3 higher-level abstractions
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Higher Reuse content at all design levels
System-Level Design
Novel design methodologies (e.g., Platform-Based
Design)
Standardization initiatives
RAISING THE ABSTRACTION LEVEL IN DESIGN
DESIGN PROCESSES
UML for specifying Design Processes (PD)
METAPROGRAMMING for specifying generic functionality
within a DP
Design Processes within
Platform-Based Design: General View
D o m a in
A n aly sis
S p ecification
M eta m od elin g
G en eratio n
A d ap tation
T a rg et system
4
Object-Oriented (OO) View to
HL Design Processes
G a te -L e ve l D e s ig n
S y s te m -L e v e l D e sig n
is
is
H a rd w a re D e s ig n
depends
depends
depends
H a rd w a re D e s ig n P ro ce ss
is
D e s ig n O p e ra tio n
5
is
*
has
1
D e s ig n P a tte rn
High-level (HL) and Low-level (LL)
Design Processes
6
UML Class Diagrams: Graphical
Notation
7
Object-Oriented (OO) View to HL
HW Design Processes: Taxonomy
Basic Operations:
Design Patterns (processes) as a specific
combination of Basic Operations:
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Refinement, Widening
Narrowing, Containment
Logical Composition, Physical Composition
Wrapping, Specialization
Composition, Recursive Composition
Example 1: Refinement
UML
A
B
VHDL
entity A is
port( x, y : in bit;
z : out bit);
end A;
architecture B of A is
begin
z <= x and y;
end B ;
Interface class is given in italic
Refinement (HW domain) = Realization (SW domain)
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Example 2: Widening
UML
A
B
VHDL
-- A is a counter without the reset signal
entity A is
port ( clk : in bit;
count : out natural);
e n d A;
-- There should be an architecture of A
-- B is a counter with the reset signal
entity B is
p o r t( c l k , r e s e t : i n b i t ;
count : out natural);
e n d B;
-- There should be an architecture of B
Widening (HW domain) = Inheritance (SW domain)
Narrowing (HW domain) = inversion of Widening (HW domain)
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Example 4: Containment
UML
A
B
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VHDL
-- There should be entity C of architecture A
archithecture A of C is
component B
port ( ...
… ) ;
end component B;
… …
begin
… …
p1: B port map ( ... ... );
… …
end A;
Containment (HW domain) = Composition (SW domain)
Example 5: Logical Composition
UML
A
VHDL
B
C
entity A is
port( X1, X2 : in bit;
Y : out bit);
end A;
entity B is
port( X3, X4 : in bit;
Z : out bit);
end B;
entity C
is
port( X1, X2, X3, X4 : in bit;
Y, Z : out bit);
end C;
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Logical Composition (HW domain) = Multiple Inheritance
(SW domain)
Example 6: Physical Composition
UML
VHDL
A
B
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C
-- There should be entity AI
-- of
architecture A
archithecture A of AI is
component B
port ( ...
… ) ;
end component B;
component C
port ( ...
… ) ;
end component C;
…
…
begin
…
…
p1: B port map ( ... ... );
p2: C port map ( ... ... );
…
…
end A;
Physical Composition (HW domain) = Composition (SW
domain)
Wrapping Design Process
UML
Block diagram
IP
H a n d sh a ke w ra p p er
R eq
W ra p p e r
D a ta _ in
A ck
H a ndsh a ke
F SM
E v n to
E n _ d a ta
R eset
IP M o d e l
W rap p e rM o d e l
D a ta _ in
IP
D a ta _ o u t
C lo ck
Wrapping Design Process (HW domain) Decorator
Design Pattern (SW domain)
For details, and VHDL code see http://soften.ktu.lt/~stuik/dac03/
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Metamodel and Transformation
from UML to VHDL (1)
UML Interface = VHDL Entity
Interface1
+attributes
-- VHDL entity corresponds to UML interface
ENTITY
Interface1 IS
PORT (
-- public attributes are used as VHDL ports
);
END
Interface1;
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Metamodel and Transformation
from UML to VHDL (2)
UML Inheritance VHDL abstraction
In te rfac e 1
+ a ttrib u tes
In te rfac e 2
-- VHDL entity corresponds to UML interface
ENTITY
Interface1 IS
PORT (
-- public attributes are used as VHDL ports
);
END
Interface1;
ENTITY
Interface2 IS
PORT (
--Interface2 inherits some ports from Interface1
--Interface2 declares some new ports
);
END
Interface2;
+ a ttrib u tes
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Inheritance (widening) is implemented using the
metaprogramming techniques
Metamodel and Transformation
from UML to VHDL (3)
UML Realization = Refinement (VHDL entityarchitecture)
In te rfac e 2
+ a ttrib u tes
C la s s
re a liza tio n
-a ttrib u tes
+m e th o d s ()
-- VHDL architecture corresponds to UML class
ARCHITECTURE
Class
OF
Interface2
IS
-- Class provides an implementation or refinement
-- for Interface2
-- private attributes are used as VHDL signals
BEGIN
-- processes are described using UML class methods
method: PROCESS()
BEGIN ... END PROCESS;
END
Class;
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Metamodel and Transformation
from UML to VHDL (4)
UML Composition = HW Containment (VHDL Port
map)
C la s s
-a ttrib u tes
+m e th o d s ()
c o m p o sitio n
ARCHITECTURE
Class
OF
Interface2
COMPONENT Interface3 IS
PORT (…, …
);
END COMPONENT Interface3 ;
IS
-- Private attributes are implemented
-- through local signals
BEGIN
method: PROCESS()
BEGIN ... END PROCESS ;
In te rfa c e 3
+ a ttrib u tes
-- Class contains component Interface3
p1: Interface3 PORT MAP ( ... );
END
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Class;
What Is a Design Process?
Design Process (DP) is:
More than a simple design pattern
A domain-specific generative process
A pattern that includes
– documentation (well-proven models, natural
language descriptions, UML diagrams), which
describes a design solution,
– domain code components, and
– tools (parsers, generators, etc.), which
implement the solution
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For properties of DPs (see paper)
Detailed Design Flow & Automatic
Generation of Instances in VHDL
W rap p er
p attern
sp ecifica tio n
U M L S tu d io
U M L m od el
(class d iagram )
p a ra m eters
U M L m eta m od el
(m ap p in g)
scrip tin g
P ragS crip t
in terp reter
tra n sla tio n
VHDL
m od el(s)
(stru ctu ral)
design
problem
dom ain know ledge
w ell-p roven
m od el(s)
M etasp ecification s
(Java + V H D L )
Java
p rocessor
p a ra m eters
th ird
party
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soft IP
(V H D L )
VHDL
p arser
T arget
system
(V H D L )
scrip t for
tran slation
in to V H D L
AST
g en era tio n
VHDL
m od el(s)
(b eh avioral)
Experimental Approval
Design Problems very close to the Real World Design
Problems we have solved:
IP Communication Problems
Based on HandShake Model
Based on FIFO Communication Model
Reliable Components (sub-systems, IPs) based on TRM
Based on SPACE redundancy
Based on DATA redundancy
Based on TIME redundancy
Third-party Soft IPs: Freely available the coarse-grained
components in VHDL (Free-6502 core, DRAGONFLY core, AX8
core, i8051 micro-controller, etc.)
Important note: All above stated design problems can be
specified using the same PD- WRAPPER DESIGN PATTERN
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Evaluation of the Approach at the
Design Process Level
HW Design Processes (DPs) reside within some
framework such as Platform-Based Design
HW designers conceive DPs usually intuitively (on
previous knowledge and design experience
basis)
In our view, DP is an abstraction (model) and it can
be treated at different levels of abstractions
A HW DP not always matches to the SW DP
(Patterns)
Perhaps (our vision) HW DPs are richer than SW
DPs
The same DP can be expressed using different
relationships
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Evaluation of the Approach at the
Specification Level
Advantages of using UML for HW design:
Difficulties of using UML for HW design relate with:
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Graphical, OO, standard, well-documented, serious efforts
for applying in HW domain now, may serve for converging
SW/HW design
High level specification (abstraction) of a designed system
Soft IP reusability, adaptability, maintainability for reuse
Specification of interconnections between components,
generic domain functionality
Model validation, increased initial development time
Relationship UML /non-OO HDL is not well-understood yet
Expressiveness of UML for HW DP is not enough
A little maturity in usage of UML for HW design
Some problems with metamodel (UML subset/VHDL
subset)
General Evaluation of the
Proposed Approach
Several problems are still left to be solved:
How to select a HDL to implement the OO
model of a system?
SystemC
(an OO HDL) is better for HW modeling,
HW/SW co-simulation and IP reuse
VHDL (not an OO HDL) is better for optimization and
synthesis
Which specification method is better for HW
design: block-based or OO?
Block
diagrams are more common for HW
designers. They are more straightforward and are
oriented at interconnecting components
UML class diagrams are more intuitive and oriented
at reusing and customizing components
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SUMMARY & CONCLUSION
We have shown that High-level Abstractions play a
key role in System-Level Design
We have introduced and discussed 3 types of
Abstractions for System-Level Design:
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Design Process as a higher-level (or meta) model
UML for Specification and Implementation of the model
MetaProgramming for generic Specification (partially)
We have (1) introduced taxonomy of UML- based
Design Processes at two levels: Operations and
Design Patterns, (2) discussed Design Flow based
on MetaModel (UML-VHDL) and its implementation
using UMLStudio Tools, and (3) evaluated the
proposed methodology
Application of UML for
Hardware Design Based on
Design Process Model
Thank You for Your attention !
http://soften.ktu.lt/~stuik/group/
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