Transcript CMOS VLSI Design CMOS VLSI Design 4th Ed.
Lecture 11: Sequential Circuit Design
Outline
Sequencing Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking
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Sequential Logic
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Sequencing
Combinational logic
– output depends on current inputs
Sequential logic
– output depends on current and previous inputs – Requires separating previous, current, future – Called
state
or
tokens
– Ex: FSM, pipeline clk clk clk clk in out CL CL CL Finite State Machine
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Pipeline
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Sequencing Cont.
If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable – Light pulses (tokens) are sent down cable – Next pulse sent before first reaches end of cable – No need for hardware to separate pulses – But
dispersion
sets min time between pulses This is called
wave pipelining
in circuits In most circuits, dispersion is high – Delay fast tokens so they don’t catch slow ones.
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Sequencing Overhead
Use flip-flops to delay fast tokens so they move through exactly one stage each cycle.
Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay – Called sequencing overhead Some people call this clocking overhead – But it applies to asynchronous circuits too – Inevitable side effect of maintaining sequence
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Sequencing Elements
Latch
: Level sensitive – a.k.a. transparent latch, D latch
Flip-flop (or Register)
: edge triggered – A.k.a. master-slave flip-flop, D flip-flop, D register Timing Diagrams – Transparent – Opaque – Edge-trigger
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Latch versus Register
Latch stores data when clock is low Register stores data when clock rises D Q Clk D Q Clk Clk D Q Clk D Q
CMOS VLSI Design 4th Ed.
Latches
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CLK D Q
Timing Definitions
t su t hold
DATA STABLE
t c 2 q
DATA STABLE
t t t Register
D Q CLK CMOS VLSI Design 4th Ed.
Characterizing Timing
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Latch Design
Pass Transistor Latch Pros + Tiny + Low clock load Cons – V t drop – nonrestoring – backdriving – output noise sensitivity – dynamic – diffusion input D Q Used in 1970’s
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Latch Design
Transmission gate + No V t drop - Requires inverted clock D Q
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Latch Design
Inverting buffer + Restoring + No backdriving + Fixes either • Output noise sensitivity • Or diffusion input – Inverted output D X D Q Q
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Latch Design
Tristate feedback + Static – Backdriving risk D X Static latches are now essential because of leakage Q
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Latch Design
Buffered input + Fixes diffusion input + Noninverting D X Q
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Latch Design
Buffered output + No backdriving D X Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 – 2 FO4 delays) - High clock loading Q
CMOS VLSI Design 4th Ed.
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Latch Design
Datapath latch + smaller + faster - unbuffered input D X Q
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Flip-Flop Design
Flip-flop is built as pair of back-to-back latches X D Q D
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X
CMOS VLSI Design 4th Ed.
Q Q
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Enable
Enable: ignore clock when en = 0 – Mux: increase latch D-Q delay – Clock Gating: increase en setup time, skew Symbol Multiplexer Design Clock Gating Design en D en Q D 1 0 en Q D Q en D en
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Q D 1 0 en Q D
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Q
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Reset
Force output low when reset asserted Synchronous vs. asynchronous D Q D Q reset reset Q reset D reset D reset D
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Q reset D reset
CMOS VLSI Design 4th Ed.
Q Q Q reset
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Set / Reset
Set forces output high when enabled D Flip-flop with asynchronous set and reset reset set set reset Q
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Sequencing Methods
T c Flip-flops 2-Phase Latches Pulsed Latches clk clk Combinational Logic clk 1 2 1 T c /2 t nonoverlap 2 Combinational Logic Half-Cycle 1 t nonoverlap Combinational Logic Half-Cycle 1 1 p t pw p p Combinational Logic
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Timing Diagrams
Contamination and Propagation Delays t pd t cd t pcq t ccq t pdq t cdq t setup t hold Logic Prop. Delay Logic Cont. Delay Latch/Flop Clk->Q Prop. Delay A Latch/Flop Clk->Q Cont. Delay Latch D->Q Prop. Delay Latch D->Q Cont. Delay Latch/Flop Setup Time Latch/Flop Hold Time D D Combinational Logic clk clk Q Q Y A Y clk D Q t cd clk t setup D Q t ccq t hold t pcq t pd t ccq t pcq t setup t cdq t pdq t hold
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Max-Delay: Flip-Flops
t pd
T c
t
setup
t pcq
sequencing overhead clk Q1 Combinational Logic T c D2 clk t setup clk t pcq Q1 D2 t pd
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Max Delay: 2-Phase Latches
t pd
t pd
1
t pd
2
T c
2
t pdq
sequencing overhead D1 1 Q1 Combinational Logic 1 D2 2 Q2 Combinational Logic 2 D3 1 Q3 1 2 T c D1 Q1 D2 Q2 D3 t pdq1 t pd1 t pdq2 t pd2
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Max Delay: Pulsed Latches
t pd
T c
max
t pdq
,
t pcq
t
setup
t pw
sequencing overhead D1 p Q1 D1 (a) t pw > t setup Q1 D2 p t (b) t pw < t setup Q1 D2 t pcq pdq Combinational Logic T c t pd t pd D2 p Q2 T c t pw t setup
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Min-Delay: Flip-Flops
t cd
t
hold
t ccq
clk Q1 CL D2 clk clk Q1 t ccq D2 t t hold cd
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Min-Delay: 2-Phase Latches
t cd
1,
t cd
2
t
hold
t ccq
t
nonoverlap 1 Q1 CL Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops.
1 2 D2 2 t nonoverlap Q1 D2 But a flop is made of two latches!
t ccq t hold t cd
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Min-Delay: Pulsed Latches
t cd
t
hold
t ccq
t pw
Hold time increased by pulse width D2 p p t pw Q1 t ccq D2 p Q1 CL t hold t cd
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Itanium 2 ALU
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Combinational Logic Delays
Element
Adder Result Mux Early Bypass Mux Middle Bypass Mux Late Bypass Mux 2 mm Wire
Propagation Delay
590 ps 60 ps 110 ps 80 ps 70 ps 100 ps
Contamination Delay
100 ps 35 ps 95 ps 55 ps 45 ps 65 ps
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Time Borrowing
In a flop-based system: – Data launches on one rising edge – Must setup before next rising edge – If it arrives late, system fails – If it arrives early, time is wasted – Flops have hard edges In a latch-based system – Data can pass through latch while transparent – Long cycle of logic can borrow time into next – As long as each loop completes in one cycle
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Time Borrowing Example
(a) (b) 1 2 1 1 2 1 Combinational Logic Combinational Logic Borrowing time across half-cycle boundary 2 Combinational Logic Borrowing time across pipeline stage boundary Combinational Logic Loops may borrow time internally but must complete within the cycle
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How Much Borrowing?
2-Phase Latches
t
borrow
T c
2
t
setup
t
nonoverlap D1 1 Q1 Combinational Logic 1 Pulsed Latches
t
borrow
t pw
t
setup 1 2 D2 T c /2 Nominal Half-Cycle 1 Delay T c t borrow D2 2 Q2 t setup t nonoverlap
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Clock Skew
We have assumed zero clock skew Clocks really have uncertainty in arrival time – Decreases maximum propagation delay – Increases minimum contamination delay – Decreases time borrowing
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Skew: Flip-Flops
t pd
T c
t pcq
t
setup
t
skew sequencing overhead
t cd
t
hold
t ccq
t
skew
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clk Q1 clk t pcq Q1 D2 clk Q1 CL D2 clk clk Q1 t ccq D2 t cd t skew t hold
CMOS VLSI Design 4th Ed.
Combinational Logic T c t pdq D2 clk t setup t skew
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Skew: Latches
2-Phase Latches
t pd
T c
2
t pdq
sequencing overhead
t cd
1 ,
t cd
2
t
hold
t ccq
t
nonoverlap
t
skew
t
borrow
T c
2
t
setup
t
nonoverlap
t
skew
t
Pulsed Latches
pd
T c
max
t pdq
,
t pcq
t
setup
t pw
t
skew sequencing overhead
t cd
t
hold
t pw
t ccq
t
skew
t
borrow
t pw
t
setup
t
skew 1 2 D1 1 Q1 Combinational Logic 1 D2 2 Q2 Combinational Logic 2 D3 1 Q3
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Two-Phase Clocking
If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important – No tools to analyze clock skew An easy way to guarantee hold times is to use 2 phase latches with big nonoverlap times Call these clocks 1 , 2 (ph1, ph2)
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Safe Flip-Flop
Past years used flip-flop with nonoverlapping clocks – Slow – nonoverlap adds to setup time – But no hold times In industry, use a better timing analyzer – Add buffers to slow signals if hold time is at risk Q X D Q
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Adaptive Sequencing
p Designers include timing margin – Voltage – Temperature – Process variation – Data dependency – Tool inaccuracies D p D Q X ERR X ERR Q Alternative: run faster and check for near failures – Idea introduced as “Razor” • Increase frequency until at the verge of error • Can reduce cycle time by ~30%
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Conventional CMOS Latches
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More CMOS Latches
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Clocked CMOS Latches
Sometimes called C 2 MOS Actually, similar to (d) in that it is tristate
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Conventional CMOS Flip-Flops
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CMOS Flip-Flops
This design has a potential race condition.
Is more likely if there is skew between the two phases of the clock.
One alternative is NORA (NO Race) flip-flop.
The other alternative is to use non-overlapping clocks.
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NORA Flip-flops
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NORA Flip-flops
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Pulse Generators
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Pulsed Latches
The Naffziger pulsed latch is used in Itanium 2 processors. It consists of the latch from (k) and the generator from (b). The pulse width is 1/6 the clock cycle.
The pulse generator of (d) is used in the NEC RISC processor.
Note that pulses are very fast and have to be distributed in the latch.
The Partovi pulsed latch (used on the AMD K6 and Athlon) builds the pulse generator into the latch.
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Pulsed Latches
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Resettable Latches and Flip-flops
There are two types of reset: – Asynchronous – Synchronous Settable latches and flip-flops force the output high rather than low.
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Resettable Latches and Flip-flops
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Asynchronous Set and Reset
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Enabled Latches and Flip-flops
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Logic in Latches
The sequencing overhead can be reduced by incorporating logic into latches.
The DEC Alpha 21164 used a whole assortment of such latches.
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Klass Semidynamic FF (SDFF)
A cross between pulsed latch and a flip-flop.
Used in Sun UltraSparc III along with built in logic.
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SDFF
Similar to the Partovi pulsed latch.
However, it uses a dynamic NAND gate.
Faster than the Partovi pulsed latch.
Worse skew tolerance and time borrowing capability.
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Differential Flip-flops
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Differential Flip-flops
The design in (a) was used in the Alpha 21164.
The SR latch formed by the NAND gates is just a salve and can be replaced by inverters if necessary.
The StrongArm 110 processor adds the weak nMOS transistor to reduce the risk when the inputs switch while the clock is high.
The AMD K6 uses the design in (b) at the interface between static and domino logic.
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Dual Edge Triggered FFs
DET flip flops have a similar thoroughput at half the clock frequency.
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DET FFs
Zhao implicitly pulsed DET FF.
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Radiation Hardened FFs
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Some Design Guides
Dynamic latches and registers have been avoided since the 0.35 m m technology node.
– Use static latches and register.
Include provisions for testing – We will study these later.
Clock distribution, especially multiple phases are problematic.
– We will study later.
Unless required performance is at the cutting edge, use registers.
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Some Design Guides
Pulsed latches are best in terms of performance.
– Remember that they have long hold times.
Extra circuitry may be necessary for short logic paths.
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Characterizing Delays
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Characterizing Delays
The set-up time cannot be crisply defined. If the data changes slightly less than a set-up time before the clock edge, the register will still capture the correct value, but its clock-Q delay will be high.
Note that
t DQ
t DC
t CQ t DQ
has a minimum when the slope of
t CQ
is
-1
.
t setup
is defined as the
t DC
at this point.
The propagation delay is the
t CQ
at this point.
The contamination delay
t ccq
is the minimum
t CQ
occurs when the input arrives early.
that The hold time is the minimum delay from clock to D
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Characterizing Delays
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Characterizing Delays
The aperture width,
t a
is the width of the window around the clock edge during which the data must not transition if the register is to produce the correct output with a propagation delay less than
t pcq
.
t t ar af
t setup
1
t hold
0
t setup
0
t hold
1
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Characterizing Delays
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Characterizing Delays
If the data arrives before the clock rises (
t DCr
must wait for the clock.
> 0
), it In this region,
t CrQ
is nearly constant and
t DQ
increases as the data arrives earlier. If the data arrives after the clock rises,
t DQ
essentially independent of arrival time.
is The data must set up before the falling edge of the clock.
If the data arrives too close to the falling edge,
t DQ
increases.
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Characterizing Delays
Choose the setup time before the knee of the curve, for example 5% greater than its minimum value.
Pulsed latches have different definitions, but they can be converter to ordinary latches by adding or subtracting pulse widths.
t setup
virtual t pcq
virtual
t setup t pdq
t pw
t pw
t pdq
virtual
t setup
t setup
virtual
t pcq
virtual t hold
virtual
t hold
t pw
t pdq
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Delay Trade-offs
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State Retention Registers
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Level Conversion
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Design Margins
Designers derate their circuits by about 30% to cope with variations.
Adaptive sequential elements seek to reduce this margin.
Dynamic voltage scaling – Precharacterize the circuit – Canary circuit – Double sampling the input
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Adaptive Sequencing
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Adaptive Sequencing
(a) shows the conceptual diagram of a razor flip-flop, while (b) is the timing diagram.
The razor flip-flop has the drawback that it may become metastable if D changes during the aperture.
An improvement is double sampling with time borrowing (DSTB).
(d) shows the Razor II pulsed latch.
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Synchronizers
A synchronizer is a circuit that accepts an input that can change at arbitrary times and produces an output aligned to its clock.
This is impossible to do in a finite time.
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Metastability
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Metastability
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Metastability
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Metastability
The cross-coupled inverters behave like an amplifier with gain
G
when
A
is near the metastable voltage
V m
.
The delay can be modeled with an RC network.
Let the initial voltage be
A
and a small offset from the metastable point be
a(0)
.
A
V m
a
C R
a
e t
s
s
G RC
1
dt
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Metastability
Assume that the node reaches a legal logic level when
V
The time to reach this level is
t DQ
s
ln
V
ln
a
Note that the speed is given by the RC time constant.
P t
DQ
T
0
e
s T c
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Synchronizers
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Synchronizers
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Synchronizers
The probability of a synchronizer failure is
N T
0
e
T c
t setu p
s T c
The mean time between failures is
MTBF
1
T c e T c
t setu p
s NT
0
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Degrees of Synchrony
Classification
Synchronous Mesosynchronous Plesiosynchronous Periodic Asynchronous
Periodic
Yes Yes Yes Yes No
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f Description
0 Constant Varies slowly Varies rapidly Unknown 0 0 Small Large Unknown Signal has same frequency and phase as clock.
Example
: register to register on chip.
Signal has same frequency, but is out of phase with clock. Safe to sample by delaying.
Example
: chip tp chip where both chips are using the same clock.
Signal has nearly the same frequency. Phase drifts slowly with time. Safe to sample signal if it is delayed by a variable, but predictable amount.
Example
: Board to board with same frequency but different crystals.
Signal is periodic at arbitrary frequency. Board to board with different crystals.
Signal changes arbitrarily.
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Asynchronous Domains
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Asynchronous Domains
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Two-Phase Handshake
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Arbiters
An arbiter decides which of the two inputs came first.
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Pipelining
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Wave Pipelining
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Schmitt Triggers
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Noise Suppression
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CMOS Schmitt Trigger
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Schmitt Trigger Simulated VTC
2.5
2.5
2.0
2.0
1.5
V M1 1.5
(V) V 1.0
0.5
V M2 V 1.0
0.5
k = 1 k = 2 k = 3 k = 4 0.0
0.0
0.5
1.0
V in (V) 1.5
2.0
2.5
Voltage-transfer characteristics with hysteresis.
0.0
0.0
0.5
1.0
1.5
2.0
V in (V) The effect of varying the ratio of the PMOS device M 4 . The width is k* 0.5 m.
2.5
CMOS VLSI Design 4th Ed.
CMOS Schmitt Trigger 2
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Multivibrator Circuits
R S
Bistable Multivibrator
flip-flop, Schmitt Trigger T
Monostable Multivibrator
one-shot
Astable Multivibrator
oscillator
CMOS VLSI Design 4th Ed.
Transition-Triggered Monostable
In
DELAY
t d Out t d
CMOS VLSI Design 4th Ed.
Monostable Trigger (RC-based)
In A R V D D B C Out
(a) Trigger circuit.
In B V M Out t t
1
t
2 CMOS VLSI Design 4th Ed.
(b) Waveforms.
Astable Multivibrators (Oscillators)
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Relaxation Oscillator
Out
1
Out
2
I
2
I
1
R Int C T
= 2 (log3)
RC
CMOS VLSI Design 4th Ed.
Voltage Controller Oscillator (VCO)
V D D M6 V contr M5 I ref In V DD M4 M2
Schmitt Trigger restores signal slopes
M1 I ref M3 Current starved inverter 6 4 2 0.0
0.5
1.5
V
co ntr (V) 2.5
propagation delay as a function of control voltage
CMOS VLSI Design 4th Ed.
Differential Delay Element and VCO
in 1 V o 2 V ctrl delay cell V o 1 in 2 3.0
2.5
V 1 V 2 V 3 V 4 2.0
1.5
1.0
0.5
0.0
2 0.5
0.5
1.5
time (ns) 2.5
3.5
simulated waveforms of 2-stage VCO
CMOS VLSI Design 4th Ed.
v 1 v 2 v 3 v 4 two stage VCO
Pitfalls and Fallacies
Incompletely reporting flip-flop delay.
Failing to check hold times.
Choosing a sequencing method too late in the design.
Failing to synchronize asynchronous inputs.
Building faulty synchronizers.
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Summary
Flip-Flops: – Very easy to use, supported by all tools 2-Phase Transparent Latches: – Lots of skew tolerance and time borrowing Pulsed Latches: – Fast, some skew tol & borrow, hold time risk
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