4 Static Operation of A Pseudo

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Transcript 4 Static Operation of A Pseudo

C H A P T E R 15 Advanced MOS and Bipolar Logic Circuits

Figure 15.1 (a)

The pseudo-NMOS logic inverter.

(b)

The enhancement-load (or saturated-load) NMOS inverter.

(c)

The depletion-load NMOS inverter.

Pseudo-NMOS Logic Circuits

 Despite many advantages, CMOS suffers from the increased area, and correspondingly increased capacitance and delay as the logic gates becomes more complex.

 For pseudo-NMOS logic inverter, only one additional transistor will be needed for each additional gate input.

This structure is similar to depleted-load NMOS but with rather improved characteristics. It also has the advantage of being directly compatible with CMOS circuits.

Static Operation of A Pseudo-NMOS Logic Inverter (1)

 The obvious disadvantage of the inverter is the non-zero V OL (point E). It causes the static power dissipation to be P D = I sat X V for V DD .

I =V DD These 2 parameters approach zero for conventional CMOS inverter.

Figure 15.2

Graphical construction to determine the VTC of the inverter in Fig. 15.1(a).

Static Operation of A Pseudo-NMOS Logic Inverter (2)

 VTC for the pseudo-NMOS inverter.

Figure 15.3

VTC for the pseudo-NMOS inverter. This curve is plotted for V,

V tn

= −

V tp

= 1 V, and

r V

= 9.

= 5

Static Operation of A Pseudo-NMOS Logic Inverter (3)

 Important parameters of the pseudo-NMOS inverter.

 The larger the value of r, the lower V OL and the wider the noise margins is are.

However, the larger

increases the asymmetry in the dynamic response and makes the gate larger for a given (W/L) P .

 Ratioed (Pseudo-NMOS) vs.

(complementary CMOS) logic circuit.

Ratioless

Dynamic Operation of A Pseudo-NMOS Logic Inverter

 The t PHL and t PLH of the pseudo-NMOS inverter are The approximation establishes for a large value of

Since k p is r times smaller than k n , t PLH will be r times larger than t PHL . Thus the circuit exhibits an asymmetrical delay performance.

Gate Circuit of A Pseudo-NMOS Logic

 4-input pseudo-NMOS NOR and NAND gates are shown below. Note that each requires only 5 transistors compared to 8 complementary CMOS.

used in   NOR type consumes less area than NAND type.

Pseudo-NMOS is suited for applications in which the output remains high most of the time.

Figure 15.4

NOR and NAND gates of the pseudo-NMOS type.

Pass-Transistor Logic Circuits (1)

 A simple approach for implementing logic functions utilizes parallel combinations of switches series and that are controlled by input variables to connect the input and output nodes.

 Each of the switches can be implemented either by a single NMOS transistor or by a pair of CMOS transistors connected in CMOS transmission gate configuration.

Y=AC CMOS transmission gate

Figure 15.6

Two possible implementations of a voltage-controlled switch connecting nodes

and

(a)

single NMOS transistor and

(b)

CMOS transmission gate.

Figure 15.5

Conceptual pass-transistor logic gates.

(a)

Two switches, controlled by the input variables

and

, when connected in series in the path between the input node to which an input variable

is applied and the output node (with an implied load to ground) realize the function

ABC

(b)

When the two switches are connected in parallel, the function realized is

(

Pass-Transistor Logic Circuits (2)

 An essential requirement in the design of pass-transistor logic is ensuring that V DD every circuit node has at all times a low-resistance path to or to ground.

 If B is high, S1 closes and Y=A.

 Y will be V DD A is low.

if A is high or ground if  If B is low, S1 opens and Y becomes a high-impedance node.

 If voltage of Y is initially zero, it will remain so.

 If voltage of Y is initially high at V DD , then the inevitable leakage current will discharge the C and can no longer be considered a static circuit.

Figure 15.7

A basic design requirement of PTL circuits is that every node have, at all times, a low resistance path to either ground or

V DD

. Such a path does not exist in

(a)

when

is low and

1 is open. It is provided in

(b)

through switch

2 .

Pass-Transistor Logic Circuits (3)

 The problem can be easily solved by establishing for node Y a low resistance path that is activated when B goes low.

 Another switch, S2, controlled by B is connected between Y and ground.

 When B goes low, S2 closes and establishes a low-resistance between Y and ground.

path

Figure 15.7

A basic design requirement of PTL circuits is that every node have, at all times, a low resistance path to either ground or

V DD

. Such a path does not exist in

(a)

when

is low and

1 is open. It is provided in

(b)

through switch

2 .

Operation with NMOS as Switches (1)

 Although switches with single NMOS transistor is a simple circuit, there are serious shortcomings in both static and dynamic performance.

 For dynamic operation ( poor “1” ): The high output voltage (V OH ) will not be equal to V DD ; rather, it will be lower by Vt , and to make matters worse, the value of Vt can be as high as 1.5 to 2 times Vto (due to body effect ).

 For static consideration , the low value of V OH can cause the Qp of the next CMOS inverter stage to conduct and thus has a finite static current and static power dissipation.

Figure 15.8

Operation with NMOS as Switches (2)

 Operation of the NMOS switch as the input goes low is shown below.

 It results in a “good 0”.

Note that the drain of an NMOS transistor is always higher in voltage than the source; correspondingly, the drain and source terminals interchange roles in comparison to previous case.

Operation with NMOS as Switches (3)

 2 methods are proposed to solve the aforementioned signal-level loss (V OH =V DD -Vt) problem.

 Circuit –based technology.

 If v O1  v O2 is high but not equal to V is low DD  Q R  turns on supplying a current to charge C to V DD .

This arrangement of Q R is somewhat involved since it creates the “positive feedback” loop around the CMOS inverter.

Fortunately, it is the “weak PMOS”.

 Process technology. If the Vt can be reduced , the signal-level loss would become less significant. Device with Vt=0 is known as natural device.

Figure 15.10

The use of transistor

Q R

, connected in a feedback loop around the CMOS inverter, to restore the

V OH

level, produced by

Q 1

, to

V DD

Microelectronic Circuits, Sixth Edition

Figure 15.11

The CMOS transmission gate and its circuit symbol.

Figure 14.12

Operation of the transmission gate as a switch in PTL circuits with

(a)

v I

high and

(b)

v I

low.

Operation with CMOS Transmission Gate as Switches (1)

 Great improvement in static and dynamic performance are obtained when the switches are implemented with CMOS transmission gate.

   Qn will stop conducting when

o = V DD -Vtn Qp will enter triode region at

o = |Vtp|, but will continue to conduct until C is fully charged and

o = V DD .

Qp provides the gate with a good “1”.

 t PLH will be lower than that in the case of single NMOS switch due to additional current available from Qp.

 Additional Qp, however, adds the value of C.

Operation with CMOS Transmission Gate as Switches (2)

 With

goes from high to low, the output waveform is shown below.

  Qp will cease conduction when

o falls to |Vtp|.

Qn, however, will continue to conduct until C is fully discharged and

o = V OL = 0V.

 The transmission gates provide far superior performance than single NMOS switches. The price paid is increased circuit complexity, area and capacitance.

Figure 15.14

(

) A transmission gate connects the output of a CMOS inverter to the input of another. (

) Equivalent circuit for the purpose of analyzing the

propagation delay

of the circuit in (

Microelectronic Circuits, Sixth Edition

Figure 15.15

A three-section

ladder network.

2 to 1 Multiplexer Using Pass-Transistor Logic (1)

 A multiplexer (MUX) is a digital switches which connects data from one of n sources to the output. A number of select inputs determine which data source is connected to the output.

2 to 1 Multiplexer Using Pass-Transistor Logic (2)

 The symbol and truth table for the 2-to-1 MUX is shown below. The circuit realizes it through pass-transistor logic is also presented.

Figure 15.16

Realization of a two-to-one multiplexer using pass-transistor logic.

Exclusive-OR Realization Using Pass-Transistor Logic

 Only 8 transistors (4 for inverter and 4 for transmission gates) are required for XOR realization.

 Note that 12 transistors are needed by using complementary CMOS .

8 transistors 12 transistors

Figure 15.17

Realization of the XOR function using pass-transistor logic.

Complementary Pass-Transistor Logic

 An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is therefore known as complementary pass-transistor logic or CPL . Note that both the output function and its complement are generated.

Figure 15.18

An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is therefore known as complementary pass-transistor logic, or CPL. Note that both the output function and its complement are generated.

Dynamic MOS Logic Circuits

 The logic circuits we have studied thus far are of the static type. That is, every node has a low resistance path to V DD or ground (the voltage of each node is well defined at all times). No node is left floating.

 Dynamic logic circuits rely on the storage of signal voltages on parasitic capacitance at certain nodes. It needs to be periodically refreshed ; thus the clock with specified minimum frequency is essential.

Features of various logic-circuit styles we have studied.

 Complementary CMOS : pros  easy to design, strong noise immunity, no static power, equal propagation delay in both directions.

cons  requirement of 2 transistors for each additional gate input.

 Pseudo-NMOS: It reduces the number of required transistors at the expense of static power dissipation.

 Pass-transistor logic: restore signal level.

It requires the use of complementary inverters to  Dynamic logic: It maintains the low device count of Pseudo-NMOS while reducing the static power to zero.

Basic Principle of Dynamic Logic Circuit

 Basic structure of dynamic-MOS logic and waveform of the clock needed to operate it.

 Precharge phase: Qp ON/ Qe OFF. V Y =V DD .

Inputs are allowed to change to proper value.

 Evaluation phase: Qp OFF/ Qe ON. If input combination makes a high output, V OH =V DD .

 Evaluation phase: Qp OFF/ Qe ON. If input combination makes a low output, the C L discharged through PDN and the V 0 V.

Y will be reduces to

Figure 15.19

(

) Basic structure of dynamic-MOS logic circuits. (

) Waveform of the clock needed to operate the dynamic logic circuit. (

) An example circuit.

An Example of Dynamic Logic Circuit

 Sizing of the PDN transistors often follows the same procedure employed in the design of static CMOS.

 For Q p , we select a W/L ratio large enough to ensure that CL will be fully charged during precharge interval.

 The size of Q p that C L should be small so will not be increased.

Figure 15.19

(

) Basic structure of dynamic-MOS logic circuits. (

) Waveform of the clock needed to operate the dynamic logic circuit. (

) An example circuit.

Microelectronic Circuits, Sixth Edition

Figure 15.20

Circuits for Example 15.3.

Non-Ideal Effects (1)

  4 major sources of non-ideal operation of dynamic logic circuits are: Noise margins: since V IL ~V IH ~Vtn, NM L =Vtn; NM H =V DD -Vtn The noise margins are far from equal and NM L is rather low.

 Output voltage decay due to leakage effects:  Without a path to ground through the PDN, the output voltage will remain high at V DD . In practice, leakage current will cause C L to discharge and the main source of such leakage leakage is the current reversed-biased junction (double for every 10 o C).

 The circuit will malfunction if the clock is operating at a very low frequency and the output is not refreshed periodically.

reversed-biased junction leakage current

Non-Ideal Effects (2)

 Charge sharing effect: For the following configuration, charge in C the capacitance between Q1/Q2 common node and ground once one of the PDN transistor turns on.

L will be shared with C1, 2 techniques to minimize the effect:  Adding a PMOS device to replenish the charge  Precharging the C1.

Increased static power dissipation Increased circuit complexity

Figure 15.21 (a)

Charge sharing.

(b)

Adding a permanently turned-on transistor

Q L

expense of static power dissipation.

solves the charge sharing problem at the

Non-Ideal Effects (3)

 Cascading dynamic logic gates: A serious problem arises if one attempts to cascade it.

 At the end of precharge, Y1 = Y2 =V DD  Ideally, during evaluation phase, if A=“1”, then Y1= “0” and Y2=“1” = V DD .

 In practice, as evaluation begins, Q1: ON, C L1 discharges discharges.

 Q2: ON, Y2 will be less than V DD .

C L2 Q2 will turn off when Y1 drops below Vtn.

Figure 15.22

Two single-input dynamic logic gates connected in cascade. With the input

high, during the evaluation phase

C L

2 partially discharge and the output at

2 will fall lower than

V DD

, which can cause logic malfunction.

will

Microelectronic Circuits, Sixth Edition

Figure E 15.10

Non-Ideal Effects (4)

Domino CMOS logic gates: The aforementioned problem when cascading the logics can be solved by the Domino CMOS logic gate .

2 single-input Domino CMOS logic gates connected in cascade.

Figure 15.23

The Domino CMOS logic gate. The circuit consists of a dynamic-MOS logic gate with a static-CMOS inverter connected to the output. During evaluation,

either will remain low (at 0 V) or will make one 0-to-1 transition (to

V DD

Non-Ideal Effects (5)

Domino CMOS logic gates: The waveforms during the evaluation phase is shown below.

 At the X1=X2=V DD end of precharge, and Y1=Y2=0.

 During the evaluation, if A= then X1  since C L1 discharges.

“1”,  Y1  (V DD ) when X1 < V IL .

 X2  since C L2 discharges.

 Y2  (V DD ) when X2 < V IL .

The propagation of the rising edge resembles contiguously placed dominos falling over, each toppling the next.

Figure 15.24 (a)

Two single-input Domino CMOS logic gates connected in cascade.

(b)

Waveforms during the evaluation phase.

Emitter-Coupled Logic –(1)

 The high speed is achieved by operating all transistors out of saturation to avoid storage time delays. In addition, the logic swing signal swings relatively small (~0.8V) to reduce the charging and discharging time.

 When v I about 4 V T is greater than V R  v O1 = V CC –I x R C by v O2 = V CC .

 When v I about 4 V T is smaller than V R  v O1 = V CC v O2 = V CC –I x R C by

Figure 15.25

The basic element of ECL is the differential pair. Here,

V R

is a reference voltage.

Emitter-Coupled Logic –(2)

 Important features of ECL:  The differential nature of the circuit makes it picked-up noise.

less susceptible to  The current drawn from the power supply remains constant during switching which produces no current spikes.

 The output signal levels are made particularly stable with V CC  both referenced to V CC = 0V.

Some means has to be provided to make the and can be output signal levels compatible with those at the input so that one gate can drive another .

 The availability of logic design with ECL .

complementary output considerably simplifies

Emitter-Coupled Logic –(3)

    ECL Families: ECL 100K: t ECL 10K : t p p ~ 0.75 ns and P D ~ 2 ns and P D ~ 40 mW  DP = 30 pJ.

~ 25 mW  DP = 50 pJ.

Slightly slower than ECL 100K but is easier to use.

 Rise and fall times are deliberately made longer for ECL 10K vs. 1 ns for ECL 100K) (edge speed 3.5 ns to reduce signal coupling.

 A variant of ECL has become popular in VLSI applications.

Microelectronic Circuits, Sixth Edition

Figure E15.12

Microelectronic Circuits, Sixth Edition

Figure 15.26

Basic circuit of the ECL 10K logic-gate family.

Emitter-Coupled Logic –(5)

 The bias network.

 The network generates a reference voltage V R temperature. V R of –1.32V at room is made to change with temperature in a predetermined manner so as to keep the noise margins almost constant.

 V R is also made relatively insensitive to variations in the power supply voltage V EE .

 Differential input stage  Paralleling input transistors (

Q A

and NOR functions.

and

Q B

) are used to implement OR  Current in of operation.

R E

remains approximately constant over the normal range  Resistances are used to connect each input terminal to the negative supply  can leave unused inputs open.

Emitter-Coupled Logic –(6)

 Emitter-follower output  On-chip loads are not included since that gate drives a line terminated at the other end in most of high-speed logic.

transmission  Emitter followers shift the level by one are centered around

V R

 Provide

v BE

drop  the shifted levels low output resistance and large current driving capability.

 Use of spikes separate power-supply prevents the coupling of from the output circuit to the gate circuit.

power-supply

Figure 15.27

The proper way to connect high-speed logic gates such as ECL. Properly terminating the transmission line connecting the two gates eliminates the “ringing” that would otherwise corrupt the logic signals. (See Section 15.4.6.)

 OR Voltage transfer characteristics  Definition of unity-gain: Q A  Assuming the v BE transistor.

(or Q R ) is conducting 1% (or 99%) of I E .

= 0.75V at a emitter current of 1mA for an ECL

Figure 15.28

Emitter-Coupled Logic –(8)

 OR Voltage transfer characteristics.

Figure 15.30

Circuit for determining

V OH

Figure 15.31

Microelectronic Circuits, Sixth Edition 15.28

Emitter-Coupled Logic –(9)

 NOR Voltage transfer characteristics.

Figure 15.31

Emitter-Coupled Logic –(10)

 Circuit for finding, range

v I > V IH .



v I

mode.

> V IH ,

Q A

v NOR

versus

v I

for the operates in the active  At point z, increments in

v I

Q A saturates.

Further cause the collector voltage to increase.

Figure 15.32

Emitter-Coupled Logic –(11)

 Manufacturers’ Specifications V ILmax : -1.475 V V IHmin = -1.105 V V OLmax : -1.630V V OHmin = -0.980V

 Fan-Out

I IL

 = (-1.77+5.2)/50 = 69 μA;

I IH

= (-0.88+5.2)/50 + 4/101 = 126 Input currents are small and output resistance is small μA  fan-out of ECL is not limited by logic-level.  The fan-out is limited by considerations of circuit speed.

 Speed  The speed is measured by the delay of its basic gate and by the rise and fall time of the output waveforms.

 The ECL gate shows shorter rise time than its fall time by using emitter follower as the output stage.

Emitter-Coupled Logic –(12)

 Signal Transmission  ECL is particularly sensitive to are so small.

ringing because the signal levels  One solution is to keep the wires signal rise/fall time  very “short” with respect to the the reflections return while the input is still rising/falling.

 If greater lengths are needed, then used  transmission lines must be the reflection is suppressed with proper termination.

Figure 15.33

Equivalent circuit for determining the temperature coefficient of the reference voltage

V R

Figure 15.34

Equivalent circuit for determining the temperature coefficient of

V OL

Figure 15.35

Equivalent circuit for determining the temperature coefficient of

V OH

Emitter-Coupled Logic –(13)

 Wired-OR Capability  The emitter follower output stage of the ECL family allows wired-OR for logic design.

 The OR function is implemented by wiring the output of several gates in parallel.

The applications of ECL include supercomputers, as well as high speed and high frequency communication system.

Figure 15.36

The wired-OR capability of ECL.

Figure 15.37

Development of the BiCMOS inverter circuit.

(a)

The basic concept is to use an additional bipolar transistor to increase the output current drive of each of

Q N

and

Q P

(c)

To reduce the turn-off times of

Q 1

of the CMOS inverter. and

Q 2

(b)

The circuit in , “bleeder resistors”

R 1

and

R 2

(a)

can be thought of as utilizing these composite devices. are added.

(d)

Implementation of the circuit in ( transistors to realize the resistors.

(e)

An improved version of the circuit in (

) obtained by connecting the lower end of

R 1

) using NMOS to the output node.

Figure 15.38

Equivalent circuits for charging and discharging a load capacitance

. Note that

includes all the capacitances present at the output node.

Microelectronic Circuits, Sixth Edition

Figure 15.39

A BiCMOS two-input NAND gate.