Transcript Why 1149.7?
Squeezing the power out of a Debug and Test Interface (DTI) IEEE P1149.7, a complementary superset of the IEEE 1149.1 standard Stephen Lau Agenda What is IEEE P1149.7? What are the benefits? How is it added to my system? How does it work? Summary 2 Stephen Lau - 12/03/07 TI Public Data What is IEEE P1149.7? What is IEEE 1149.1 (JTAG)? Connection for manufacturing test (BSDL) Connection for debugging software 3 Stephen Lau - 12/03/07 TI Public Data Standards Focus 1149.1 vs. P1149.7 Test 1149.1 P1149.7 Boundary Scan: Finding card level connectivity issues Compliance: Preserving boundary scan for System on a Chip (SoC) Capability: Features for debug Apps 4 Stephen Lau - 12/03/07 TI Public Data What is IEEE P1149.7? What is IEEE 1149.1 (JTAG)? Connection for manufacturing test (BSDL) Connection for debugging software What is IEEE P1149.7? 5 A new IEEE standard currently in process P1149.7 is not a replacement for 1149.1 P1149.7 uses 1149.1 as its foundation P1149.7 provides 1149.1 extensions P1149.7 provides 2-pin operating modes Stephen Lau - 12/03/07 TI Public Data P1149.7 History and Status MIPI Origins Objective – define a backwards compatible minimum pin debug interface Strategy – requirements gathering, technical debate Tactics – solicit competing proposals, choose a winner Result – P1149.7 was handily selected as winning proposal vs. SWD Collaboration with Nexus consortium Objective – Compare common needs, explore common solution Strategy - Joint meetings, compare requirements Tactics - Specifications reviewed, incorporate feedback Result – Agreement to pursue IEEE standard because of large field of use IEEE PAR approved Test, Debug, and backwards IEEE 1149.1 compatibility considerations Specification reviewed and revision underway now Presumed Result – IEEE 1149.7 standard in early 2008 6 Stephen Lau - 12/03/07 TI Public Data What are the benefits? Innovation / Customization Preserve Investment Do more with less Feature 7 Benefit Operate with fewer pins Fewer pins required for debug/test Add instrumentation using the same pins Application level debug TAP power management Do more with Reduce less power consumption Provide framework for diverse debug technologies Improve compatibility Preserve gateway to debug of SI errors/defects Maintain capabilties SI IP Re-use proven technology Re-use proven technology Preserve Investment Software IP Debug and Test Tools Re-use proven technology Pin protocols other than those supporting scan Support for existing technology Backward compatible Innovation / Customization Mix and match legacy/new IP Equal treatment for all industry IP Stephen Lau - 12/03/07 Support for existing technology TI Public Data Extending JTAG JTAG Pins Required=6 Emulator 8 TCLK TCLK TMS TMS TDI TDI TDO TDO EMU0 EMU0 EMU1 EMU1 Stephen Lau - 12/03/07 TI Public Data EMU1 EMU0 TDO TCLK TMS TDI EMU1 Core B EMU0 TDO TCLK SW Driver TMS TDI Core A Extending JTAG JTAG Pins Required=6 Core A Communication (4) Emulator Instrumentation (2) TCLK TCLK TMS TMS TDI Read Mem TDI TDO TDO EMU0 EMU0 EMU1 EMU1 •IEEE1149.1 example: Data path is from TDI through cores and out TDO. 9 Stephen Lau - 12/03/07 TI Public Data EMU1 EMU0 TDO TCLK TMS TDI EMU1 EMU0 TDO TCLK TMS 0xcoffee TDI SW Driver Core B Extending JTAG 4 JTAG JTAG Pins Pins Required= Required=6 TCLK TMS Emulator TCLK Switch to 1149.7 TMS TCLK TCLK TMSC TMS TMS TDI TDI TDI TDI TDO TDO TDO TDO EMU0 EMU0 EMU0 EMU0 EMU1 EMU1 EMU1 EMU1 Mode=JTAG Mode=advanced •Use adapters to prototype with existing IEEE1149.1 HW and SW. •IEEE1149.7 starts in 1149.1 mode for compatibility. •Switch the Adapter to IEEE1149.7 mode by sending a command. 10 Stephen Lau - 12/03/07 TI Public Data •TMS is now TMSC. •TDI and TDO are now optional. Optional signal EMU1 EMU0 TDO TCLK TMS TDI EMU1 Core B EMU0 TDO TCLK SW Driver TMS TDI Core A Extending 1149.1 2 4 Pins Required= Emulator TCLK TCLK TMS TMS TDI TDI TDO TDO EMU0 EMU0 EMU1 EMU1 EMU1 EMU0 TDO TCLK TMS TDI EMU1 Core B EMU0 TDO TCLK SW Driver TMS TDI Core A TCLK 0xcoffee TMSC TMS TDI TDO 0xcoffee EMU0 EMU1 Mode=Advanced •EMU0 and EMU1 are typically used for to gather large amounts communication with a target application •Using Background Data eXchange (BDX) and Custom Data eXchange (CDX), target information can be transferred. •For maximum compatibility, CDX can be used to carry manufacturer defined protocols. 11 Stephen Lau - 12/03/07 TI Public Data Extending 1149.1 2 Pins Required= Emulator TCLK TCLK TMSC TMSC TMS TDI TDI TDO TDO EMU0 EMU0 EMU1 EMU1 Mode=Advanced 12 Stephen Lau - 12/03/07 TI Public Data EMU1 EMU0 TDO TCLK TMS TDI EMU1 Core B EMU0 TDO TCLK SW Driver TMS TDI Core A IEEE P1149.7 Connection Topologies 4-pin Series Scan Topology TDI DTC Interface 4-pin Star Scan Topology T T T T C MD D K S I O T T TDI C M TDO K S TCK TMS TCK TDI TMS DTC Interface TDO TDO T T TDO C M TDI K S T T T T C M D D K S I O 2-pin Star Scan Topology When all chips have Class 4 or Class 5 TAPs the 4-pin topologies may be operated as a 2-pin topology T T C M K S DTC Interface TCK TMS TCK TMS T T C M K S 13 Stephen Lau - 12/03/07 TCK TMS TDI TDO TCK TMS TDI TDO TI Public Data Key Control Concepts Extend functionality of BYPASS and IDCODE instructions (“overload” these instructions) Keep new command structure invisible to existing 1149.1 TAPs Create commands without using TDI or TDO Use commands to create registers without changing IR/DR scan paths 14 Stephen Lau - 12/03/07 TI Public Data Overloading the Bypass Instruction (using Zero-bit DR-Scans (ZBS)) Method: • IR register set to BYPASS or IDCODE instruction by: • IR-Scan or • Test-Logic-Reset • ZBS = CaptureExitUpdate • The number of consecutive ZBSs are counted to create a control level that specifies the overloaded function • This is performed by standard IEEE 1149.1 TAP controller state sequences IR Register 15 BYPASS Stephen Lau - 12/03/07 TI Public Data Zero-Bit Scans Create Control Levels Key: • Count the number of ZeroBit-Scans (ZBS) to change the definition of BYPASS instruction. 1…. 2…. 3…. Lock Control Level at 3. 16 Stephen Lau - 12/03/07 IR Register BYPASS TI Public Data • Lock control level when the Shift-DR state is reached. Creating a Control Level Example: Steps to create a control level 3 1. 2. 3. 4. IR-Scan with BYPASS instr. ZBS ZBS ZBS BYPASS instruction Increment control level from 0 to 1 Increment control level from 1 to 2 Increment control level from 2 to 3 Example: Steps to create a control level 5 1. 2. 3. 4. 5. 6. 17 IR-Scan with BYPASS instr. ZBS ZBS ZBS ZBS ZBS Stephen Lau - 12/03/07 TI Public Data BYPASS instruction Increment control level from 0 to 1 Increment control level from 1 to 2 Increment control level from 2 to 3 Increment control level from 3 to 4 Increment control level from 4 to 5 IEEE1149.7 - Debug and Test Tech. Binder “All industry debug and test IP co-exists behind a standard Interface” Standard interface JTAG benefits tools suppliers and users Applications TAPs 1149.7 Narrow (2) or Wide (4) 18 Boundary Scan Debug/Test Framework BDX Bulk Data Transfer Instrumentation Sources CDX Custom Data Transfer BDM (Freescale)/ SWD (ARM)/other Power Power down test logic when not used Test Test and Private Interface Modes IEEE 1149.1 signaling used at start-up SW directed mode switches between JTAG modes and advanced modes. Software drivers always use IEEE state sequences. SW directed mode switches between JTAG modes and advanced modes Framework for multiple debug and other technologies Stephen Lau - 12/03/07 TI Public Data Deployment Profiles JTAG Optimized serialization of TMS, TDI, Ready, and TDO Multiple formats BDX Pause and Idle states provide instrumentation channel Pin and BW Utilization CDX Shift_DR state may be used to overlay any custom protocol Extensibility (non-JTAG functions) Power Chip power and reset controller managing interface power Every microwatt counts Test Test and private interface modes Specialty functions Deployment Profile Minimal Flash, CPLDs, FPGAs 19 Stephen Lau - 12/03/07 Moderate SOC or Micro-Controller TI Public Data Most Sophisticated SOC 1149.7 “Classes” IEEE 1149.1 Extensions Class T0 – Assure IEEE Compliance for chips with multiple TAPs Class T1 – Add control functions (e.g. functional reset, power) Class T2 – Add performance features for series Class T3 – Add Star configuration Advanced Two-Pin Operation Class T4 – Add two pin operation Class T5 – Add instruction/custom pin use to two pin operation 20 Stephen Lau - 12/03/07 TI Public Data IEEE 1149.7 Summary Do More with Less: Lower pin count Remaining backwards compatible with Si IP and Tools Gain additional debug capability 21 Stephen Lau - 12/03/07 TI Public Data Backup Stephen Lau IEEE 1149.7 Classes Class T0 • Ensure compliance with 1149.1 to enhance compatibility with industry test infrastructure • After Test-Logic-Reset (TLR) multi-TAP devices: • Conform to mandatory 1149.1 instruction behavior • 1-bit DR-Scan for bypass instruction • Addresses stacked die and multi-chip module needs Class T1 • Power: Test logic power-down, etc. • Chip Level Bypass Class T2 • Performance: •Shorten multi-chip scan chains with 1-bit IR bypass Class T3 •Glue-less star configuration • Built-in Chip Select Mechanism Class T4 • Pins: Less pins and more functions •Faster downloads to target •Equivalent performance with fewer pins • 2 pins provide scan, Test-Logic-Reset (TLR), and instrumentation (serialized transactions) • Download specific modes (Target Input only) • 2x Clock rate and optimized transactions • Instrumentation (BDX) • Concurrent Debug and Instrumentation using same pins • Instrumentation of data passed during Run-TestIdle, Pause-DR, and Pause-IR states • Custom technologies can use the test access port pins in Shift-DR state. (ex: SWD, BDM, etc. ) Class T5 • Customization (CDX) 23 Stephen Lau - 12/03/07 • 4 Power Down modes friendly to: Board Test, Chip Test, and Application Debug TI Public Data P1149.7 – Adds capability to 1149.1 “Minimizing Changes/Maintaining Performance” • The same or better performance than IEEE1149.1 may be achieved in some cases • With advanced protocol • Falling–edge to falling edge timing allows doubling TCK rate • The amount of information transferred is minimized to boost performance • Two or less bits are transferred/TAP controller state in some cases •If a device supports SSCAN modes, performance can improve more. 2*TCK rate 1.7 1 21.5 bits/TAP bits/TAP bits/TAP bits/TAP state state state state =2X 1.17X the TCK/TAP state rate as IEEE 1149.1 the same TCK/TAP state rate as IEEE 1149.1 = = 1.3X the the TCK/TAP TCK/TAP state state rate rate as as IEEE IEEE 1149.1 1149.1 Existing controller 24 Emulator 1149.7 logic IEEE 1149.7 added May be added to existing controller Stephen Lau - 12/03/07 20 MHz 40 MHz 20 MHz Chip 1149.7 logic Narrow (2-pins) or Wide (4-pins) TI Public Data Existing Si IP IEEE 1149.7 added No changes to existing Si IP Series Bypass Uses TAP selection and bypass bit to: improve series conneted devices scan performance using 1-bit chip bypass for very long scan chains Create a “firewall” to protect system operation when DTC is connected or disconnected from the TS TAP1 TAP2 TAP1 TAP2 TAP1 38-bit IR 24-bit IR 16-bit IR 16-bit IR 6-bit IR TAP1 and TAP2 frozen in IDLE state. 1-bit bypass Chip Level Bypass 25 Stephen Lau - 12/03/07 TAP1 and TAP2 frozen in IDLE state. 1-bit bypass Chip Level Bypass TI Public Data TAP1 6-bit IR I want to access this one! Total Chain =100 Total Chain =8 Situation at Power-Up At power up, you can have the bypass as the default (JScan1 scan format) Protects TAPs from spurious signal Prevents core corruption during “hot” connections Command sequence makes TAPs visible. Command sequence is transparent to IEEE1149.1 devices allowing a mix of IEEE1149.1 and IEEE1149.7 devices. Configuration at Power UP 1149.7 Device TAP1 and TAP2 frozen in TLR state. 1-bit bypass 1-bit bypass 1149.7 Device Configuration after “firewall” lowered. 26 1149.7 Device TAP1 and TAP2 frozen in TLR state. 1149.1 Device TAP1 6-bit IR 1149.7 Device 1149.1 Device TAP1 TAP2 TAP1 TAP2 TAP1 38-bit IR 24-bit IR 16-bit IR 16-bit IR 6-bit IR Stephen Lau - 12/03/07 TI Public Data