Transcript 28nm Platform Leadership Announcement Messaging

Zynq-7000 EPP Introduction
Where ARM Processors Meet HW Programmability
May 2012
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Demands of Today's Technology
EPP
FPGA
ASSP
Structured
ASIC
Which Technology Should I Choose?
Page 2
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
ASIC
Current Selections Equal Compromise
Performance
Power
Unit Cost
ASIC
ASSP
+
+
+
+
+
+
+
+
+
-
TCO

Risk
-
TTM
Flexibility
Scalability
2 Chip
Solution

+ positive, - negative,  neutral
Conflicting Demands Not Served
Page 3
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011

+
+
+
+
+
Introducing the Zynq™-7000 EPP
Breakthrough Processing Platform
– Higher system performance, lower total power
– Flexible and scalable solution
Industry Standard Design Environments
– Well defined SW programming model
– Familiar SW & HW design flows
Flexible Accelerators and IP
– World class 28nm programmable logic architecture
– Standard AMBA® 4 AXI interfaces
Broad Ecosystem Support
– Tools, OS’s & IPs
– Middleware, codecs
– System integrators and training partners.
Familiar Processing System + Scalable Programmable Logic
Page 4
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Zynq-7000 Extensible Processing Platform
Next level of Programmable System Integration into a true SoC
– All programmable (software and hardware) processing platform
– ARM Cortex™-A9 MPCore™ Processing System with hardened peripherals,
ADC and 28nm scalable optimized programmablel ogic
c
Increased System Performance
– 800 MHz, dual core processors with NEON and vector floating point units
– 7 series programmable logic (PL) with built-in DSP
– High bandwidth, low latency connects enable acceleration of key functions
BOM Cost Advantage in an cost optimized 28nm platform
– Integration saves components, area and simplifies PCB
– Platform approach enables aggregation of volumes over several projects
Lower Total Power solution
– Industry-leading ARM processors maximize MHz/W and low power states
– 28nm HPL process and Integration provides ultra-lower power data transfers
Accelerated Design Productivity for TTM and TIM advantage
– Industry standard HW and SW development tools for fast Time-To-Market
– Flexible and scalable platform enables extended Time-In-Market
– Extensive ecosystem of tools and solutions partners
Page 5
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Zynq-7000 Family Highlights
Complete ARM®-based Processing System
– Dual ARM Cortex™-A9 MPCore™, processor centric
– Integrated memory controllers & peripherals
– Fully autonomous to the programmable logic
Tightly Integrated Programmable Logic
– Used to extend processing system
Processing
System
Common
Peripherals
Memory
Interfaces
ARM®
Dual Cortex-A9
MPCore™ System
– High performance AXI based Interface
– Scalable density and performance
Common Accelerators
Custom Accelerators
Flexible Array of I/O
– Wide range of external multi-standard I/O
– High performance integrated serial transceivers
– Analog-to-Digital Converter inputs
Software & Hardware Programmable
Page 6
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
7 Series
Programmable
Logic
Common
Peripherals
Custom
Peripherals
Zynq-7000 Device Portfolio Summary
Scalable Platform offers easy migration between devices
Zynq-7000 EPP Devices
Z-7010
Z-7020
Processing System
Programmable
Logic
NEON™ & Single / Double Precision Floating Point
Processor Extensions
Max Frequency
800MHz
Memory
L1 Cache 32KB I / D, L2 Cache 512KB, on-chip Memory 256KB
External Memory Support
Approximate ASIC Gates
Extensible Block RAM
Peak DSP Performance (Symmetric FIR)
DDR3, DDR2, LPDDR2, 2x QSPI, NAND, NOR
2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet,
2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
~430K (30k LC)
~1.3M (85k LC)
~1.9M (125k LC)
~5.2M (350k LC)
240KB
560KB
1,060KB
2,180KB
58 GMACS
158 GMACS
480 GMACS
1080 GMACS
Gen2 x4
Gen2 x8
PCI Express® (Root Complex or Endpoint)
-
Agile Mixed Signal (XADC)
2x 12bit 1Msps A/D Converter
I/O
Processor System IO
Page 7
Multi Standards 3.3V IO
Z-7045
Dual ARM® Cortex™-A9 MPCore™
Processor Core
Peripherals
Z-7030
130
100
200
100
212
Multi Standards High Performance 1.8V IO
-
-
150
150
Multi Gigabit Transceivers
-
-
4
16
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Delivering Highest Customer Value
Build better
processing
systemsfaster
with fewer chips … faster
Build
better systems
Accelerated Design Productivity
Increased System
Performance
BOM Cost
Reduction
Total Power
Reduction
Programmable Systems Integration
Page 8
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Programmable Systems Integration
Accelerated Design Productivity
Increased
System
Performance
BOM Cost
Reduction
Total Power
Reduction
Programmable Systems Integration
ALL Programmable Platform Integrating Multiple Components
– Hardware and Software programmable
– Board component reduction
– Security & reliability
– Manufacturing benefits
Defines Extensibility
– Create custom, flexible ASSP
– Co-processing offload by accelerating software functions
ARM Programmability + FPGA Flexibility in a Single Chip
Page 9
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Increased System Performance
Accelerated Design Productivity
Increased
System
Performance
BOM Cost
Reduction
Total Power
Reduction
Programmable Systems Integration
Hardware Performance
– Dual Core ARM Cortex A9’s with NEON and
vector floating point
– High performance programmable logic
– Tightly coupled processor and programmable logic
• High throughput / low latency
– Massive parallel DSP processing
– High performance I/Os and transceivers (12.5Gbps)
Accelerating Processor Performance
– Increasing software performance through co-processing
accelerators
– Low latency interfacing for efficient co-processor
implementation
Elements
Performance
(up to)
Processors (each)
800 MHz
Processors (aggregate)
4000 DMIPs
DSP (each)
600MHz
DSP (aggregate)
1080 GMACs
Transceivers (each)
12.5Gbps
Transceivers (aggregate)
200Gbps
SW Acceleration using PL
>10x
Optimized Balance of Performance and Power
Page 10
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
BOM Cost Reduction
Accelerated Design Productivity
Increased
System
Performance
BOM Cost
Reduction
Total Power
Reduction
Programmable Systems Integration
Reduced Devices per Board
Up to 40% BOM Cost
Reduction vs. MultiChip Solutions
– Processors, PLDs, DSPs
– Power supplies, fans, etc…
BOM Cost
– A/D converters
FPGA
Reduced PCB Complexity
DSP
Processor
– Fewer traces/interconnect/layers
– Fewer power supplies
EPP
PCB / Other
Components
– Smaller overall PCB
Multi-chip
Zynq-7000
In System Reconfiguration Combines Multiple Device Functions
– HW can be configured and reconfigured only with the needed function at a given time
PS Aggregates Numerous IP Royalties for Net Cost Benefit
– ASIC or full FPGA solutions would require purchase of these IPs from 3rd parties.
Platform approach enables aggregation of volumes for lower price
Page 11
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Total Power Reduction
Accelerated Design Productivity
Increased
System
Performance
BOM Cost
Reduction
Total Power
Reduction
Programmable Systems Integration
Flexible/Tunable Power Envelope
– Adjustable processor speed
– Adjustable ARM AMBA®- AXI & memory
speeds
– ARM low power states
– Programmable logic can be turned off
– Programmable logic clock gating
– Partial reconfiguration to reduce
Programmable logic requirement
Up to 50% Lower Power
Vs. Multi-Chip Solutions
FPGA
Integration Power Reduction
– Reduced interconnections between devices
DSP
– Fewer system devices
EPP
– Lower programmable logic power (28nm HPL process)
Processor
Multi-chip
Significant Power Reduction at the System Level
Page 12
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Zynq-7000
Accelerated Design Productivity
Accelerated Design Productivity
Increased
System
Performance
BOM Cost
Reduction
Total Power
Reduction
Programmable Systems Integration
Reduced Time To Market
– Fixed processor system across family
– Scalable optimized architecture for IP re-use / AXI interfaces for plug & play IP
– Accelerate developments with targeted design platforms
ASIC /
ASSP /
2 Chip
Increased Time In Market
Dev.
Design #1
Dev.
Design #2
– Software and hardware re-programmability
Dev.
– Field upgradable
Design #3
– Address ASSPs short shelf life
EPP
Dev.
Industry Leading Tools
Platform #1
Dev.
Dev.
– Development tools
• Xilinx platform studio (XPS), software developers Kit (SDK),
IDS for programmable logic development and PS configuration
• Support for 3rd party SW tools – (any Cortex-A9 tool should just work)
– Development platforms
Application
• Emulation platform, virtual platform, development boards
Extensive Ecosystem
Market-Specific
Domain-Specific
– Strong and rapidly growing global partner and other 3rd party support
– Industry leading OS’s, tools, IP, system integration/design houses
Page 13
Extended Product life
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Base Platform
Zynq-7000 EPP Value Proposition
ASIC
ASSP
+
+
+
+
Unit Cost
+
TCO

Risk
-
+
+
+
Performance
Power
TTM
Flexibility
Scalability
+

+ positive, -
2 Chip
Solution
Zynq-7000

+
+
+
+
+
negative,  neutral
Conflicting Demands Now Served by the Zynq-7000 Family
Page 14
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
+
+

+
+
+
+
+
Designing with Zynq-7000 EPP
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Zynq-7000 EPP Platform Offering
Libraries & APIs
Virtual Platform
Silicon
Reference Design & Board
OS BSP’s
Applications
OS Kernel
High Level and Low Level Drivers
Processing System
SW Development
Tools
SW & HW IP
Custom
Programmable
Logic
HW Development
Tools
More Than Just Silicon – A Comprehensive Platform Offering.
Page 16
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Developments Environments
End-to-End Tools
Industry-leading
Tools
– Xilinx SDK
– ARM Ecosystem
– Open Source
– High Level Synthesis
– VHDL/Verilog: From
Design Entry to
Implementation
– Simulation
– Timing, power, signal
analysis
Huge SW Base
–
–
–
–
–
Xilinx
Open Source
ARM libraries
RTOS and OS vendors
Middleware
Many Sources of HW
IP
–
–
–
–
–
Page 17
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Xilinx Library
3rd Party
Custom
High Level Functions
Standardized around AXI
Zynq-7000 EPP SW Development Environment
ARM-standard Development
with Xilinx Flexibility
Leverage ARM Worldwide Ecosystem
–
–
–
–
–
Silicon
– Standard ARM Instruction Set and APIs
– AXI support
– Easy software migration from
other ARM-based systems
OS BSP’s
Applications
Libraries & APIs
OS Kernel
High Level and Low Level Drivers
Processing System
Tools
OS, Middleware, Libraries
Professional Services
3rd Party
Open Source Community
Board Support Package, Drivers and Custom IP Cores
– Provided for a range of development boards, peripherals
and system functions
Page 18
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Custom
Programmable Logic
Zynq-7000 EPP HW Design Environment
Customize your Design
OS BSP’s
Create a unique microprocessor configuration
Realize DSP, graphics, communications functions
Design custom accelerators and functions
Deploy high level functions directly to silicon
Silicon
–
–
–
–
Applications
Xilinx-Optimized EDA Design tools
– HDL & HLS simulation
– HDL synthesis
– Design analysis
Integrate Plug & Play IP Portfolio
– AMBA® AXI enabled
– Large selection of Xilinx and 3rd Party IP
Page 19
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Libraries & APIs
OS Kernel
High Level and Low Level Drivers
Processing System
Custom
Programmable Logic
Zynq-7000 EPP Development Platforms
Powerful Xilinx Development Platforms
– ZC702 Base Evaluation Kit
– Zynq-7000 EPP Video Kit
– Many Application Specific Development Kits
– Expandable with Industry Standards FMC
(FPGA Mezzanine Connector) Daughter Cards
– QEMU Virtual Platform
Various Partner development Platforms
– Community based AVNET ZedBoard
– Many local and worldwide COTS providers
– Cadence Virtual Platform
Page 20
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Extensive Partnership Ecosystem
And MORE …
Page 21
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Zynq-7000 EPP – Platform Availability
HW Design Tools
• ISE Design Suite 14.1
Virtual Platform
Tools Ecosystem
3 options:
•QEMU,
•Software Developer
•System Creator
OS Ecosystem
Other partners
•Linux, Android, WinCE,
VxWorks, ENEA OSE,
FreeRTOS, …
• IP FPGA Blocks
•Software elements
•Design Services (Boards
and Applications)
•Trainings
Silicon Devices
Page 22
Dev. Boards
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Zynq-7000 Extensible Processing Platform
Summary
New Scalable Family of Devices
– Zynq-7000 EPP device portfolio
– Four devices for a broad range of applications
Industry Standard Design Environments
– Well defined SW programming model
– Familiar HW design flow
– Flexible accelerators and IP
– Standard AMBA® AXI interfaces
Broad and Expanding Ecosystem
– Tools, OS’s, IP
– Middleware, codecs …
Availability
– Z-7020 Sampling Now
– Production 2H CY2012
Page 23
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Zynq-7000 EPP Driver Assistance Application
Page 24
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Zynq-7000 EPP Broadcast Camera Application
Page 25
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Zynq-7000 EPP Broadcast Camera Application
Page 26
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Device Table
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Zynq-7000 Device Table
Processing System
Zynq™-7000 Extensible Processing Platform
Device Name
Z-7010
Z-7020
Z-7030
Z-7045
Part Number
XC7Z010
XC7Z020
XC7Z030
XC7Z045
Dual ARM® Cortex™-A9 MPCore™ w ith CoreSight™
Processor Core
Processor Extensions
NEON™ & Single / Double Precision Floating Point for each processor
Processing System
Maxim um Frequency
800 MHz
L1 Cache
32 KB Instruction, 32 KB Data per processor
L2 Cache
512 KB
On-Chip Mem ory
256 KB
External Mem ory Support
DDR3, DDR2, LPDDR2
External Static Mem ory Support
2x Quad-SPI, NAND, NOR
DMA Channels
8 (4 dedicated to Programmable Logic)
2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
Peripherals
Peripherals w / built-in DMA
Security(1)
Processing System to Program m able Logic Interface Ports
(Prim ary Interfaces & Interrupts Only)
Page 28
2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO
AES and SHA 256b Decryption and Authentication for Secure Boot
2x AXI 32b Master, 2x AXI 32b Slave,
4x AXI 64b/32b Memory
See next slide for Programmable Logic and package details
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011
Zynq-7000 Device Table
Programmable Logic and Packages
Zynq™-7000 Extensible Processing Platform
Device Name
Z-7010
Z-7020
Z-7030
Z-7045
Part Number
XC7Z010
XC7Z020
XC7Z030
XC7Z045
Programmable Logic
Xilinx 7 Series Program m able Logic Equivalent
Program m able Logic Cells (Approxim ate ASIC Gates (3))
Artix™-7 FPGA
Artix™-7 FPGA
Kintex™-7 FPGA
Kintex™-7 FPGA
28K Logic Cells (~430K)
85K Logic Cells (~1.3M)
125K Logic Cells (~1.9M)
350K Logic Cells (~5.2M)
218,600
Look-Up Tables (LUTs)
17,600
53,200
78,600
Flip-Flops
35,200
106,400
157,200
437,200
240 KB (60)
560 KB (140)
1,060 KB (265)
2,180 KB (545)
Extensible Block RAM (# 36 Kb Blocks)
80
220
400
900
58 GMACS
158 GMACS
480 GMACS
1080 GMACS
—
—
Gen2 x4
Gen2 x8
Program m able DSP Slices (18x25 MACCs)
Peak DSP Perform ance (Sym m etric FIR)
PCI Express® (Root Com plex or Endpoint)
2x 12 bit, MSPS ADCs w ith up to 17 Differential Inputs
Agile Mixed Signal (AMS) / XADC
Security(1)
-1
Speed
Grades
-2, -3
Extended (0C to 100C)
-1, -2
Industrial (-40C to 100C)
Package Type (4)
Packages
AES and SHA 256b Decryption and Authentication for Secure Programmable Logic Configuration
Com m ercial (0C to 85C)
CLG400
CLG400
CLG484
FBG484
FBG676
FFG676
FBG676
FFG676
FFG900
Size (m m )
17x17
17x17
19x19
23x23
27x27
27x27
27x27
27x27
31x31
Pitch (m m )
0.8
0.8
0.8
1.0
1.0
1.0
1.0
1.0
1.0
Processing System User I/Os (Excludes DDR dedicated I/Os) (2)
Multi-Standards and Multi-Voltage SelectIOTM Interfaces
(1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V)
Multi-Standards and Multi-Voltage High Perform ance SelectIO
Interfaces
(1.2V, 1.35V, 1.5V, 1.8V)
Serial Transceivers
54
54
54
54
54
54
54
54
54
100
125
200
100
100
100
100
100
212
—
—
—
63
150
150
150
150
150
Maxim um Transceiver Speed (Speedgrade Dependant)
—
—
—
4
4
4
8
8
16
N/A
N/A
N/A
6.6 Gb/s
6.6 Gb/s
12.5 Gb/s
6.6 Gb/s
12.5 Gb/s
12.5 Gb/s
Notes: 1. Security block is shared by the Processing System and the Programmable Logic.
2. Static memory interface combined w ith the usage of many peripherals could require more than 54 I/Os. In that case the designer can use the Programmable Logic SelectIO interface.
3. Eqivalent ASIC gate count is dependent of the function implemented. The assumption is 1 Logic Cell = ~15 ASIC Gates.
4. Devices in the same package are pin to pin compatible, FBG676 and FFG676 are also pin to pin compatible
5. Preliminary product information. Subject to change. Please contact your Xilinx representative for the latest information
Page 29
Copyright 2011 Xilinx
© Copyright
2009Xilinx
Xilinx
Copyright
2011