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State of the art in FPGA technology Jecel Assumpção Jr LCR - ICMC - USP São Carlos

• Xilinx vs Altera • Bit players • Rookies • Alternatives topics

• First FPGA (1985) • Sells US$1.7B/year • First reprogrammable logic device (1984) • First CPLD (1988) • Sells US$1.2B/year QuickTime™ and a decompressor are needed to see this picture.

• High End = Virtex • 1998 • 1999 E • 2000 II • 2002 II Pro • 2004 4 LX/SX/FX • 2006 5 LX/LXT/SXT • 2008 5 FXT/TXT • 2009 6 Xilinx vs Altera • High End = Stratix • 2002 • 2003 GX • 2004 II • 2005 II GX • 2006 III • 2008 IV E • 2008 IV GX

• Low End = Spartan • 1998 • 1999 II • 2001 IIE • 2003 3 • 2005 3E • 2006 3A • 2007 3AN/3A-DSP • 2009 6 Xilinx vs Altera • Low End = Cyclone • 2003 • 2004 II • 2007 III • 2009 IV

technology Logic cells Block RAM DSP Tranceivers I/O speed Xilinx vs Altera Virtex 6 40nm 75K to 588K 6M to 33M 288 to 864 Up to 48+24 380 to 720 600MHz Stratix IV 40nm 72K to 803K 7M to 33M 384 to 1024 Up to 48 372 to 920 600MHz

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Bit player: Lattice • ECP3 - lowest cost FPGA with SERDES • XP2 - 90nm Flash • Also ECP2, ECP2M and SC

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Bit player: Actel • Igloo and ProASIC3 - low power • SmartFusion and Fusion - mixed signal • RTAX, RTProASIC3 and RTSX - radiation tolerance • Axcelerator, SX-A, eX and MX - antifuse

Bit player: QuickLogic • Customer Specific Standard Products (CSSPs)

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Bit player: Atmel • Legacy devices - AT6000 • AT40KAL + AVR8 = FPSLIC (Field Programmable System Level Integrated Circuits)

Edinburgh • 1985 to 1988 - three generations of CAL up to CAL256 • 1989 - Algotronix formed, CAL1024 • 1993 - bought by Xilinx: XC6200 • Very popular for research, but not commercially

Imperial College QuickTime™ and a decompressor are needed to see this picture.

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Rookie: Silicon Blue • Classic architecture • Low power • Low cost • Internal Flash

Rookie: Achronix • 1.5GHz

• picoPIPE assynchronous internal architecture • SERDES • DDR3 controllers

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Rookie: Tabula • 1.6GHz with 8 multiplexed designs • 48 SERDES • 5.5MB RAM • 220K to 630K logic cells

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Rookie: Tier Logic QuickTime™ and a decompressor are needed to see this picture.

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Alternative: eASIC • Standard Cell ASIC-like unit cost, power consumption performance and density • Low up-front development cost • Simple, FPGA-like design flow • Device turnaround in only 4-6 weeks

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Alternative: Stretch Inc QuickTime™ and a decompressor are needed to see this picture.

Alternative: Trips QuickTime™ and a decompressor are needed to see this picture.

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Alternative: Xmos QuickTime™ and a decompressor are needed to see this picture.

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Alternative: MathStar QuickTime™ and a decompressor are needed to see this picture.

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Alternative: Tilera QuickTime™ and a decompressor are needed to see this picture.

Alternative: Stream Processors Inc QuickTime™ and a decompressor are needed to see this picture.

Thanks!

references • • • • • http://www.xilinx.com/ http://www.altera.com/ http://lms.nthu.edu.tw/sys/read_attach.php?i

d=17968 http://ce.et.tudelft.nl/FPL/trimbergerFPL2007.

pdf http://www.fpga guide.com/overview_frame.html

references • • • • • • http://www.latticesemi.com/ http://www.actel.com/ http://www.quicklogic.com/ http://www.atmel.com/ http://www.algotronix.com/people/tom/albu m.html

http://www.doc.ic.ac.uk/~ipage/papers/cam9 5.pdf

references • • • • http://www.siliconbluetech.com/ http://www.achronix.com/ http://www.tabula.com/ http://www.tierlogic.com/

references • • • • • • • http://www.easic.com/ http://www.stretchinc.com/ http://userweb.cs.utexas.edu/~trips/ http://www.xmos.com/ http://www.mathstar.com/ http://www.tilera.com/ http://www.streamprocessors.com/